Trong-Thuc Hoang
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
20
Venues
3
Active years
2016–2025
Best venue rank
C
Where they publish
Papers
20 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | Compact FALCON FFT/NTT Accelerator for Post-Quantum Cryptography. | Duc-Thuan Dam, Thai-Ha Tran, Trong-Hung Nguyen, Trong-Thuc Hoang, Cong-Kha Pham |
| 2025 | ISCAS | A Low-Latency Polynomial Arithmetic Unit for ML-KEM and ML-DSA Standards. | Trong-Hung Nguyen, Duc-Thuan Dam, Phuc-Phan Duong, Trong-Thuc Hoang, Cong-Kha Pham |
| 2025 | ISCAS | Live Demonstration: ASIC Implementation of ASCON Lightweight Cryptography for IoT Applications. | Khai-Duy Nguyen, Tuan-Kiet Dang, Binh Kieu-Do-Nguyen, Cong-Kha Pham, Trong-Thuc Hoang |
| 2025 | ISCAS | Enhanced Tower Field Mask Scheme with Affine Transformation-based Dynamic S-box. | Thai-Ha Tran, Duc-Thuan Dam, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham |
| 2024 | ICCSA | Designing and Implementing a 2D Integer DCT Hardware Accelerator Fully Compatible with Versatile Video Coding. | Nhu-Hoang Nguyen, Tan-Phat Dang, Thanh-Dat Bui, Trong-Thuc Hoang, Cong-Kha Pham, Huu-Thuan Huynh |
| 2024 | ISCAS | A Strong 4 4 S-Box Using an Enhanced Tent Map. | Phuc-Phan Duong, Trong-Thuc Hoang, Cong-Kha Pham |
| 2024 | ISCAS | Unified-pipelined NTT Architecture for Polynomial Multiplication in Lattice-based Cryptosystems. | Trong-Hung Nguyen, Nguyen The Binh, Huynh Phuc Nghi, Cong-Kha Pham, Trong-Thuc Hoang |
| 2024 | ISCAS | A Unified OTP and PUF Exploiting Post-Program Current on Standard CMOS Technology. | Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Khai-Duy Nguyen, Tetsuya Iizuka, Trong-Thuc Hoang, Cong-Kha Pham |
| 2024 | ISCAS | An Efficient Hiding Countermeasure with Xilinx MMCM Primitive in Spread Mode. | Thai-Ha Tran, Van-Phuc Hoang, Duc-Hung Le, Trong-Thuc Hoang, Cong-Kha Pham |
| 2024 | PST | An Efficient Method for Accelerating Kyber and Dilithium Post-Quantum Cryptography. | Duc-Thuan Dam, Trong-Hung Nguyen, Thai-Ha Tran, Binh Kieu-Do-Nguyen, Trong-Thuc Hoang, Cong-Kha Pham |
| 2024 | PST | Hardware Implementation of a Hybrid Dynamic Gold Code-Based Countermeasure Against Side-Channel Attacks. | Thai-Ha Tran, Duc-Thuan Dam, Binh Kieu-Do-Nguyen, Van-Phuc Hoang, Trong-Thuc Hoang, Cong-Kha Pham |
| 2023 | ISCAS | In-NVRAM Unified PUF and TRNG Based on Standard CMOS Technology. | Ronaldo Serrano, Marco Sarmiento, Ckristian Duran, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham |
| 2022 | ISCAS | Spectre attack detection with Neutral Network on RISC-V processor. | Anh-Tien Le, Trong-Thuc Hoang, Ba-Anh Dao, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
| 2020 | ISCAS | Cryptographic Accelerators for Trusted Execution Environment in RISC-V Processors. | Trong-Thuc Hoang, Ckristian Duran, Akira Tsukamoto, Kuniyasu Suzaki, Cong-Kha Pham |
| 2019 | ISCAS | Live Demonstration: Real-Time Auto-Exposure Histogram Equalization Video-System using Frequent Items Counter. | Takahiro Hosaka, Trong-Thuc Hoang, Van-Phuc Hoang, Duc-Hung Le, Katsumi Inoue, Cong-Kha Pham |
| 2019 | ISCAS | A 1.2-V 90-MHz Bitmap Index Creation Accelerator with 0.27-nW Standby Power on 65-nm Silicon-On-Thin-Box (SOTB) CMOS. | Xuan-Thuan Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Ngoc-Tu Bui, Van-Phuc Hoang, Cong-Kha Pham |
| 2018 | ISCAS | High-speed 8/16/32-point DCT Architecture Using Fixed-rotation Adaptive CORDIC. | Trong-Thuc Hoang, Cong-Kha Pham, Duc-Hung Le |
| 2018 | ISCAS | A 219-μW 1D-to-2D-Based Priority Encoder on 65-nm SOTB CMOS. | Xuan-Thuan Nguyen, Trong-Thuc Hoang, Hong-Thu Nguyen, Katsumi Inoue, Cong-Kha Pham |
| 2016 | ISCAS | A hybrid adaptive CORDIC in 65nm SOTB CMOS process. | Trong-Thuc Hoang, Duc-Hung Le, Hong-Thu Nguyen, Xuan-Thuan Nguyen, Cong-Kha Pham |
| 2016 | ISCAS | An efficient FPGA-based database processor for fast database analytics. | Xuan-Thuan Nguyen, Hong-Thu Nguyen, Trong-Thuc Hoang, Katsumi Inoue, Osamu Shimojo, Toshio Murayama, Kenji Tominaga, Cong-Kha Pham |