| 2025 | DAC | Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced Packaging. | Min-Hung Chen, Cheng-Yen Li, Chuan-Chi Su, Yao-Wen Chang, Tung-Chieh Chen |
| 2025 | ICCAD | CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs. | Jingyu Pan, Isaac Jacobson, Zheng Zhao, Tung-Chieh Chen, Guanglei Zhou, Chen-Chia Chang, Vineet Rashingkar, Yiran Chen |
| 2024 | ICCAD | Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules. | Yu-Yang Chen, Yi-Chen Lin, Tzu-Han Hsu, Iris Hui-Ru Jiang, Tung-Chieh Chen, Tai-Chen Chen, Hua-Yu Chang |
| 2022 | DAC | Flexible chip placement via reinforcement learning: late breaking results. | Fu-Chieh Chang, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-Shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen |
| 2021 | DAC | VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units. | Yun Chou, Jhih-Wei Hsu, Yao-Wen Chang, Tung-Chieh Chen |
| 2019 | ASPDAC | MDP-trees: multi-domain macro placement for ultra large-scale mixed-size designs. | Yen-Chun Liu, Tung-Chieh Chen, Yao-Wen Chang, Sy-Yen Kuo |
| 2018 | ASPDAC | FastPass: Fast timing path search for generalized timing exception handling. | Pei-Yu Lee, Iris Hui-Ru Jiang, Tung-Chieh Chen |
| 2017 | ICCAD | A novel damped-wave framework for macro placement. | Chin-Hao Chang, Yao-Wen Chang, Tung-Chieh Chen |
| 2017 | ICCAD | An integrated-spreading-based macro-refining algorithm for large-scale mixed-size circuit designs. | Szu-To Chen, Yao-Wen Chang, Tung-Chieh Chen |
| 2017 | ICCAD | Blockage-aware terminal propagation for placement wirelength minimization. | Sheng-Wei Yang, Yao-Wen Chang, Tung-Chieh Chen |
| 2015 | ASPDAC | An approach to anchoring and placing high performance custom digital designs. | Shih-Ying Liu, Tung-Chieh Chen, Hung-Ming Chen |
| 2013 | DAC | Double patterning lithography-aware analog placement. | Hsing-Chih Chang Chien, Hung-Chih Ou, Tung-Chieh Chen, Ta-Yu Kuan, Yao-Wen Chang |
| 2013 | DAC | Routability-driven placement for hierarchical mixed-size circuit designs. | Meng-Kai Hsu, Yi-Fang Chen, Chau-Chin Huang, Tung-Chieh Chen, Yao-Wen Chang |
| 2013 | ICCAD | Efficient analog layout prototyping by layout reuse with routing preservation. | Ching-Yu Chin, Po-Cheng Pan, Hung-Ming Chen, Tung-Chieh Chen, Jou-Chun Lin |
| 2012 | ICCAD | Performance-driven analog placement considering monotonic current paths. | Po-Hsun Wu, Mark Po-Hung Lin, Yang-Ru Chen, Bing-Shiun Chou, Tung-Chieh Chen, Tsung-Yi Ho, Bin-Da Liu |
| 2011 | ICCAD | Fast analog layout prototyping for nanometer design migration. | Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen |
| 2008 | DAC | An integrated nonlinear placement framework with congestion and porosity aware buffer planning. | Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan |
| 2007 | DAC | MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs. | Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Fwu-Juh Huang, Denny Liu |
| 2006 | ICCAD | A high-quality mixed-size analytical placer considering preplaced blocks and density constraints. | Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang |
| 2005 | ASPDAC | SoC test scheduling using the B-tree based floorplanning technique. | Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang |
| 2005 | ICCAD | IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs. | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |