Tuo-Hung Hou
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
4
Active years
2015–2024
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2024 | DATE | A Multi-Bit Near-RRAM based Computing Macro with Highly Computing Parallelism for CNN Application. | Kuan-Chih Lin, Hao Zuo, Hsiang-Yu Wang, Yuan-Ping Huang, Ci-Hao Wu, Yan-Cheng Guo, Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang |
| 2023 | ISCAS | FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices. | Yan-Cheng Guo, Wei-Tien Lin, Tuo-Hung Hou, Tian-Sheuan Chang |
| 2020 | ISCAS | Methodology for Realizing VMM with Binary RRAM Arrays: Experimental Demonstration of Binarized-ADALINE using OxRAM Crossbar. | Sandeep Kaur Kingra, Vivek Parmar, Shubham Negi, Sufyan Khan, Boris Hudec, Tuo-Hung Hou, Manan Suri |
| 2019 | DAC | NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge. | Chih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou |
| 2015 | ICCAD | Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip Learning. | Pai-Yu Chen, Binbin Lin, I-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu |