Valerio Tenace
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
9
Venues
3
Active years
2014–2026
Best venue rank
A*
Where they publish
Papers
9 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | DATE | Special Day - A Design Blueprint for Scalable Multi-Agent Architectures in Complex EDA Workflows. | Valerio Tenace, Pierre-Emmanuel Gaillardon |
| 2025 | DATE | EDA-Aware RTL Generation with Large Language Models. | Mubashir ul Islam, Humza Sami, Pierre-Emmanuel Gaillardon, Valerio Tenace |
| 2021 | DATE | Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. | Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jnata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee |
| 2019 | DATE | Energy-Efficient Convolutional Neural Networks via Recurrent Data Reuse. | Luca Mocerino, Valerio Tenace, Andrea Calimera |
| 2019 | DATE | SAID: A Supergate-Aided Logic Synthesis Flow for Memristive Crossbars. | Valerio Tenace, Roberto Giorgio Rizzo, Debjyoti Bhattacharjee, Anupam Chattopadhyay, Andrea Calimera |
| 2018 | ISCAS | Multiplication by Inference using Classification Trees: A Case-Study Analysis. | Roberto Giorgio Rizzo, Valerio Tenace, Andrea Calimera |
| 2016 | ISCAS | Enabling quasi-adiabatic logic arrays for silicon and beyond-silicon technologies. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2015 | DAC | One-pass logic synthesis for graphene-based Pass-XNOR logic circuits. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |
| 2014 | DATE | Pass-XNOR logic: A new logic style for P-N junction based graphene circuits. | Valerio Tenace, Andrea Calimera, Enrico Macii, Massimo Poncino |