Veena Yelamanchili
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2004–2004
Best venue rank
A*
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | DAC | Fast and accurate parasitic capacitance models for layout-aware. | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |
| 2004 | DATE | Accurate Estimation of Parasitic Capacitances in Analog Circuits. | Anuradha Agarwal, Hemanth Sampath, Veena Yelamanchili, Ranga Vemuri |