Veerapaneni Nagbhushan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2007–2008
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2008 | ICCD | Modeling and reduction of complex timing constraints in high performance digital circuits. | Veerapaneni Nagbhushan, C. Y. Roger Chen |
| 2007 | ICCD | Algorithms to simplify multi-clock/edge timing constraints. | Veerapaneni Nagbhushan, C. Y. Roger Chen |