Viresh Paruthi
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
14
Venues
4
Active years
1998–2015
Best venue rank
A*
Where they publish
Papers
14 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2015 | DATE | Designer-level verification: an industrial experience story. | Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru |
| 2014 | DAC | Automatic Verification of Floating Point Units. | Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky |
| 2012 | FMCAD | Formal verification of error correcting circuits using computational algebraic geometry. | Alexey Lvov, Luis Alfonso Lastras-Montao, Viresh Paruthi, Robert Shadowen, Ali El-Zein |
| 2011 | FMCAD | Hybrid verification of a hardware modular reduction engine. | Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony |
| 2010 | FMCAD | Formal verification of arbiters using property strengthening and underapproximations. | Gadiel Auerbach, Fady Copty, Viresh Paruthi |
| 2010 | FMCAD | Large-scale application of formal verification: From fiction to fact. | Viresh Paruthi |
| 2009 | FMCAD | Formal verification of correctness and performance of random priority-based arbiters. | Krishnan Kailas, Viresh Paruthi, Brian Monwai |
| 2006 | ICCD | Scalable Sequential Equivalence Checking across Arbitrary Design Transformations . | Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen |
| 2005 | DAC | Exploiting suspected redundancy without proving it. | Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman |
| 2005 | DATE | Automatic Formal Verification of Fused-Multiply-Add FPUs. | Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner |
| 2004 | FMCAD | Scalable Automated Verification via Expert-System Guided Transformations. | Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann |
| 2001 | DAC | Circuit-based Boolean Reasoning. | Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi |
| 2000 | ICCD | Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation. | Viresh Paruthi, Andreas Kuehlmann |
| 1998 | ICCD | Automatic data path abstraction for verification of large scale designs. | Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri |