| 2025 | DATE | Multi-Partner Project: A Model-Driven Engineering Framework for Federated Digital Twins of Industrial Systems (MATISSE). | Alessio Bucaioni, Romina Eramo, Luca Berardinelli, Hugo Bruneliere, Benot Combemale, Djamel Eddine Khelladi, Vittoriano Muttillo, Andrey Sadovykh, Manuel Wimmer |
| 2025 | MODELS | Coupling LLMs and Model-Driven Engineering to Support Synthetic Generation of BPMN Artifacts. | Vittoriano Muttillo, Romina Eramo, Riccardo Rubei, Luca Berardinelli |
| 2024 | ICCD | SLIDE-x-ML: System-Level Infrastructure for Dataset E-xtraction and Machine Learning Framework for High-Level Synthesis Estimations. | Vittoriano Muttillo, Vincenzo Stoico, Marco Santic, Giacomo Valente, Luigi Pomante, Daniele Frigioni |
| 2021 | DSD | AIDOaRt: AI-augmented Automation for DevOps, a Model-based Framework for Continuous Development in Cyber-Physical Systems. | Romina Eramo, Vittoriano Muttillo, Luca Berardinelli, Hugo Bruneliere, Abel Gmez, Alessandra Bagnato, Andrey Sadovykh, Antonio Cicchetti |
| 2020 | DSD | Run-time Monitoring and Trace Analysis Methodology for Component-based Embedded Systems Design Flow. | Vittoriano Muttillo, Giacomo Valente, Luigi Pomante, Hector Posadas, Javier Merino, Eugenio Villar |
| 2019 | DSD | HW/SW Co-Design Framework for Mixed-Criticality Embedded Systems Considering Xtratum-Based SW Partitions. | Vittoriano Muttillo, Luigi Pomante, Patricia Balbastre, Jos E. Sim, Alfons Crespo |
| 2018 | DSD | Design Space Exploration for Mixed-Criticality Embedded Systems Considering Hypervisor-Based SW Partitions. | Vittoriano Muttillo, Giacomo Valente, Luigi Pomante |
| 2016 | PDP | A Flexible Profiling Sub-System for Reconfigurable Logic Architectures. | Giacomo Valente, Vittoriano Muttillo, Luigi Pomante, Fabio Federici, Marco Faccio, Andrea Moro, Serenella Ferri, Carlo Tieri |