| 2023 | DATE | Processor Verification using Symbolic Execution: A RISC-V Case-Study. | Niklas Bruns, Vladimir Herdt, Rolf Drechsler |
| 2023 | FDL | Identification of ISA-Level Mutation-Classes for Qualification of RISC-V Formal Verification. | Milan Funck, Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
| 2023 | ICAART | Coverage-Guided Fuzzing for Plan-Based Robotics. | Tim Meywerk, Vladimir Herdt, Rolf Drechsler |
| 2022 | ASPDAC | Automated Detection of Spatial Memory Safety Violations for Constrained Devices. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | ATVA | SISL: Concolic Testing of Structured Binary Input Formats via Partial Specification. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2022 | DAC | Verifying SystemC TLM peripherals using modern C++ symbolic execution tools. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2022 | DATE | Cross-Level Processor Verification via Endless Randomized Instruction Stream Generation with Coverage-guided Aging. | Niklas Bruns, Vladimir Herdt, Eyck Jentzsch, Rolf Drechsler |
| 2022 | DATE | The Scale4Edge RISC-V Ecosystem. | Wolfgang Ecker, Peer Adelt, Wolfgang Mller, Reinhold Heckmann, Milos Krstic, Vladimir Herdt, Rolf Drechsler, Gerhard Angst, Ralf Wimmer, Andreas Mauderer, Rafael Stahl, Karsten Emrich, Daniel Mueller-Gritschneder, Bernd Becker, Philipp Scholl, Eyck Jentzsch, Jan Schlamelcher, Kim Grttner, Paul Palomero Bernardo, Oliver Bringmann, Mihaela Damian, Julian Oppermann, Andreas Koch, Jrg Bormann, Johannes Partzsch, Christian Mayr, Wolfgang Kunz |
| 2022 | DDECS | Virtual Prototype driven Design, Implementation and Evaluation of RISC-V Instruction Set Extensions. | Milan Funck, Vladimir Herdt, Rolf Drechsler |
| 2022 | DSD | Task Mapping and Scheduling in FPGA-based Heterogeneous Real-time Systems: A RISC-V Case-Study. | Sallar Ahmadi-Pour, Sangeet Saha, Vladimir Herdt, Rolf Drechsler, Klaus D. McDonald-Maier |
| 2022 | FDL | Unified HW/SW Coverage: A Novel Metric to Boost Coverage-guided Fuzzing for Virtual Prototype based HW/SW Co-Verification. | Niklas Bruns, Vladimir Herdt, Rolf Drechsler |
| 2022 | FDL | Virtual Prototype based Analysis of Neural Network Cache Behavior for Tiny Edge Device. | Alexander Fratzer, Vladimir Herdt, Christoph Lth, Rolf Drechsler |
| 2022 | FDL | 3D Visualization of Symbolic Execution Traces. | Jan Zielasko, Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | ASPDAC | Mutation-based Compliance Testing for RISC-V. | Vladimir Herdt, Sren Tempel, Daniel Groe, Rolf Drechsler |
| 2021 | DAC | Towards Reliable Spatial Memory Safety for Embedded Software by Combining Checked C with Concolic Testing. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | DATE | Vertical IP Protection of the Next-Generation Devices: Quo Vadis? | Shubham Rai, Siddharth Garg, Christian Pilato, Vladimir Herdt, Elmira Moussavi, Dominik Sisejkovic, Ramesh Karri, Rolf Drechsler, Farhad Merchant, Akash Kumar |
| 2021 | DATE | An Effective Methodology for Integrating Concolic Testing with SystemC-based Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2021 | FDL | RISC-V AMS VP: An Open Source Evaluation Platform for Cyber-Physical Systems. | Sallar Ahmadi-Pour, Vladimir Herdt, Rolf Drechsler |
| 2021 | FDL | In-Vivo Stack Overflow Detection and Stack Size Estimation for Low-End Multithreaded Operating Systems using Virtual Prototypes. | Sren Tempel, Vladimir Herdt, Rolf Drechsler |
| 2020 | ATVA | RVX - A Tool for Concolic Testing of Embedded Binaries Targeting RISC-V Platforms. | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Closing the RISC-V Compliance Gap: Looking from the Negative Testing Side | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DAC | Dynamic Information Flow Tracking for Embedded Binaries using SystemC-based Virtual Prototypes. | Pascal Pieper, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Fast and Accurate Performance Evaluation for RISC-V using Virtual Prototypes | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | DATE | Towards Specification and Testing of RISC-V ISA Compliance | Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2020 | FDL | Efficient Cross-Level Testing for Processor Verification: A RISC- V Case-Study. | Vladimir Herdt, Daniel Groe, Eyck Jentzsch, Rolf Drechsler |
| 2020 | ICCD | Adaptive Simulation with Virtual Prototypes for RISC-V: Switching Between Fast and Accurate at Runtime. | Vladimir Herdt, Daniel Groe, Sren Tempel, Rolf Drechsler |
| 2020 | ISoLA | Verifying Safety Properties of Robotic Plans Operating in Real-World Environments via Logic-Based Environment Modeling. | Tim Meywerk, Marcel Walter, Vladimir Herdt, Jan Kleinekathfer, Daniel Groe, Rolf Drechsler |
| 2019 | ASPDAC | Maximizing power state cross coverage in firmware-based power management. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2019 | DAC | Early Concolic Testing of Embedded Binaries with Virtual Prototypes: A RISC-V Case Study. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DATE | Verifying Instruction Set Simulators using Coverage-guided Fuzzing | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2019 | DSD | Towards Formal Verification of Plans for Cognition-Enabled Autonomous Robotic Agents. | Tim Meywerk, Marcel Walter, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2019 | FDL | Systematic RISC-V based Firmware Design | Vladimir Herdt, Daniel Groe, Rolf Drechsler, Christoph Gerum, Alexander Louis-Ferdinand Jung, Joscha Benz, Oliver Bringmann, Michael Schwarz, Dominik Stoffel, Wolfgang Kunz |
| 2018 | DATE | Towards fully automated TLM-to-RTL property refinement. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2018 | DATE | Resilience evaluation via symbolic fault injection on intermediate code. | Hoang M. Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2018 | FDL | Extensible and Configurable RISC-V Based Virtual Prototype. | Vladimir Herdt, Daniel Groe, Hoang M. Le, Rolf Drechsler |
| 2017 | DATE | Data flow testing for virtual prototypes. | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Mingsong Chen, Daniel Groe, Rolf Drechsler |
| 2017 | FDL | Towards early validation of firmware-based power management using virtual prototypes: A constrained random approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | FDL | Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2017 | ICCAD | Early SoC security validation by VP-based static information flow analysis. | Muhammad Hassan, Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | CAV | ParCoSS: Efficient Parallelized Compiled Symbolic Simulation. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2016 | DATE | Towards formal verification of real-world SystemC TLM peripheral models - a case study. | Hoang Minh Le, Vladimir Herdt, Daniel Groe, Rolf Drechsler |
| 2016 | FDL | On the application of formal fault localization to automated RTL-to-TLM fault correspondence analysis for fast and accurate VP-based error effect simulation - a case study. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2016 | ICCAD | Compiled symbolic simulation for systemC. | Vladimir Herdt, Hoang M. Le, Daniel Groe, Rolf Drechsler |
| 2015 | ATVA | Lazy-CSeq-SP: Boosting Sequentialization-Based Verification of Multi-threaded C Programs via Symbolic Pruning of Redundant Schedules. | Vladimir Herdt, Hoang Minh Le, Daniel Groe, Rolf Drechsler |
| 2015 | DAC | Verifying SystemC using stateful symbolic simulation. | Vladimir Herdt, Hoang Minh Le, Rolf Drechsler |
| 2013 | DAC | Verifying SystemC using an intermediate verification language and symbolic simulation. | Hoang Minh Le, Daniel Groe, Vladimir Herdt, Rolf Drechsler |