| 2017 | DATE | Formal model for system-level power management design. | Mirela Simonovic, Vojin Zivojnovic, Lazar Saranovac |
| 1999 | DAC | Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification. | Lisa M. Guerra, Joachim Fitzner, Dipankar Talukdar, Chris Schlger, Bassam Tabbara, Vojin Zivojnovic |
| 1999 | DAC | LISA - Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures. | Stefan Pees, Andreas Hoffmann, Vojin Zivojnovic, Heinrich Meyr |
| 1997 | ICASSP | An upper bound of the throughput of multirate multiprocessor schedules. | Rainer Schoenen, Vojin Zivojnovic, Heinrich Meyr |
| 1997 | ICASSP | Modulo-addressing utilization in automatic software synthesis for digital signal processors. | Markus Willems, Holger Keding, Vojin Zivojnovic, Heinrich Meyr |
| 1997 | ICASSP | Minimum Fisher information spectral analysis. | Vojin Zivojnovic, Dominikus Noll |
| 1996 | DAC | Compiled HW/SW Co-Simulation. | Vojin Zivojnovic, Heinrich Meyr |
| 1996 | ICASSP | Hierarchization of a priori defined dataflow subgraphs. | Markus Willems, Vojin Zivojnovic, Sebastian Ritz |
| 1996 | ICASSP | On retiming of multirate DSP algorithms. | Vojin Zivojnovic, Rainer Schoenen |
| 1994 | ICASSP | Retiming of DSP programs for optimum vectorization. | Vojin Zivojnovic, Sebastian Ritz, Heinrich Meyr |
| 1993 | ISCAS | Design of optimum interpolation filters for digital demodulators. | Vojin Zivojnovic, Heinrich Meyr |