| 2013 | DDECS | A GHz full-division-range programmable divider with output duty-cycle improved. | Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang |
| 2009 | DDECS | 0.5V 160-MHz 260uW all digital phase-locked loop. | Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng |
| 2008 | DDECS | A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. | Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw |
| 2007 | ISCAS | New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. | Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien |
| 2006 | ISCAS | The new improved pseudo fractional-N clock generator with 50% duty cycle. | Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang |
| 2005 | ISCAS | A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. | Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang |
| 2004 | ISCAS | A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. | Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo |
| 2001 | ISCAS | A low-power high driving ability voltage control oscillator used in PLL. | Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung |