Wei-Hao Chiu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
1
Venues
1
Active years
2010–2010
Best venue rank
C
Where they publish
Papers
1 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2010 | ISCAS | A 5-GHz fractional-N phase-locked loop with spur reduction technique in 0.13-μm CMOS. | Wei-Hao Chiu, Chien-Yuan Cheng, Tsung-Hsien Lin |