Weiguang Sheng
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
15
Venues
8
Active years
2008–2026
Best venue rank
A*
Where they publish
Papers
15 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ASPDAC | Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. | Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2025 | DAC | Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator. | Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing |
| 2025 | DATE | HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. | Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng |
| 2024 | ISCAS | A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. | Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing |
| 2023 | ASPDAC | An Efficient near-Bank Processing Architecture for Personalized Recommendation System. | Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng |
| 2023 | ICCD | ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. | Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang |
| 2021 | DATE | Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. | Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng |
| 2021 | DATE | Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. | Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing |
| 2019 | ISPASS | mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. | Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna |
| 2018 | DATE | Optimizing the data placement and transformation for multi-bank CGRA computing system. | Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao |
| 2018 | FAST | Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. | Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li |
| 2017 | DATE | A static-placement, dynamic-issue framework for CGRA loop accelerator. | Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li |
| 2015 | PRDC | Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. | Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao |
| 2009 | DAC | Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. | Weiguang Sheng, Liyi Xiao, Zhigang Mao |
| 2008 | PRDC | Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. | Weiguang Sheng, Liyi Xiao, Zhigang Mao |