| 2025 | DAC | EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog Circuits. | Jian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao, Xuan Zhang |
| 2025 | DAC | Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMs. | Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin |
| 2025 | ICCAD | Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision. | Weimin Fu, Shijie Li, Kaichen Yang, Xuan Silvia Zhang, Yier Jin, Xiaolong Guo |
| 2025 | ISCAS | Enhancing LLM Performance on Hardware Design Generation Task via Reinforcement Learning. | Yifang Zhao, Weimin Fu, Shijie Li, Yixiang Hu, Xiaolong Guo, Yier Jin |
| 2024 | ASPDAC | Hardware Phi-1.5B: A Large Language Model Encodes Hardware Domain Specific Knowledge. | Weimin Fu, Shijie Li, Yifang Zhao, Haocheng Ma, Raj Gautam Dutta, Xuan Zhang, Kaichen Yang, Yier Jin, Xiaolong Guo |
| 2024 | CCS | Poster: Enhance Hardware Domain Specific Large Language Model with Reinforcement Learning for Resilience. | Weimin Fu, Yifang Zhao, Yier Jin, Xiaolong Guo |
| 2022 | DATE | Inter-IP Malicious Modification Detection through Static Information Flow Tracking. | Zhaoxiang Liu, Orlando Arias, Weimin Fu, Yier Jin, Xiaolong Guo |