Won-Joo Yun
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2009–2013
Best venue rank
C
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2013 | ISCAS | A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL. | Yuki Urano, Won-Joo Yun, Tadahiro Kuroda, Hiroki Ishikuro |
| 2010 | ISCAS | A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface. | Hyun-Woo Lee, Yong-Hoon Kim, Won-Joo Yun, Eun Young Park, Kang Youl Lee, Jaeil Kim, Kwang Hyun Kim, Jongho Jung, Kyung Whan Kim, Nam Gyu Rye, Kwan-Weon Kim, Jun Hyun Chun, Chulwoo Kim, Young-Jung Choi, Byong-Tae Chung, Joong Sik Kih |
| 2009 | ISCAS | A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter. | Dongsuk Shin, Jabeom Koo, Won-Joo Yun, Young-Jung Choi, Chulwoo Kim |