| 2021 | ISCAS | A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. | Dong Yanchi, Weixin Gai, Xiao Xiang, Haowei Niu |
| 2019 | ISCAS | Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. | Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang |
| 2019 | ISCAS | An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. | Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng |
| 2018 | ISCAS | A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. | Linqi Shi, Weixin Gai, Jichao Huang, Liangxiao Tang, Xiao Xiang |
| 2018 | ISCAS | An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. | Linqi Shi, Weixin Gai, Xiaoting Zhi, Liangxiao Tang, Xiao Xiang |
| 2017 | ISCAS | A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. | Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang |
| 2016 | ISCAS | A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier. | Shihao Li, Weixin Gai, Xiao Xiang, Liangxiao Tang, Jichao Huang, Tong Zhao, Xiaoting Zhi |
| 2014 | VTC | Measurement and Modeling of the LTE Train-Ground Channel for High-Speed Railway in Viaduct Scenario. | Ruojun Zhao, Muqing Wu, Xiao Xiang, Jiaqi Yang |