| 2026 | ISCAS | PRIMAL: Processing-In-Memory based Low-Rank Adaptation for LLM Inference Accelerator. | Yue Jiet Chong, Yimin Wang, Zhen Wu, Xuanyao Fong |
| 2026 | ISCAS | LOKI: An LLM Accelerator with Optimized KV Cache and In-Memory Computing Cores. | Avadh Harkishanka, Abhishek Tyagi, Xuanyao Fong |
| 2026 | ISCAS | Topology-Mapping Co-Design for Scalable LLM Accelerators with Hierarchical Mesh-of-Trees NoC. | Zhen Wu, Yimin Wang, Yue Jiet Chong, Xuanyao Fong |
| 2026 | ISCAS | Cross-Layer Evaluation for On-Chip Training of BEOL FeTFT-based CIM M3D Accelerator. | Wei Zhang, Jianze Wang, Yimin Wang, Xuanyao Fong |
| 2025 | AAAI | Massively Parallel Continuous Local Search for Hybrid SAT Solving on GPUs. | Yunuo Cen, Zhiwei Zhang, Xuanyao Fong |
| 2025 | ICCAD | LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism. | Yimin Wang, Yue Jiet Chong, Xuanyao Fong |
| 2025 | ISCAS | A Pseudo-Boolean Encoding Method for Rectilinear Steiner Arborescence in VLSI Routing. | Zixuan Wang, Yunuo Cen, Xuanyao Fong |
| 2024 | ISCAS | Design Framework for Ising Machines with Bistable Latch-Based Spins and All-to-All Resistive Coupling. | Yimin Wang, Yunuo Cen, Xuanyao Fong |
| 2024 | ISCAS | Energy-Efficient Ising Machines Using Capacitance-Coupled Latches for MaxCut Solving. | Yimin Wang, Xuanyao Fong |
| 2024 | ISCAS | Transposable Memory Based on the Ferroelectric Field-Effect Transistor. | Jianze Wang, Wei Zhang, Zhen Wu, Yimin Wang, Leming Jiao, Xiaolin Wang, Xiao Gong, Xuanyao Fong |
| 2023 | IJCNN | A Semi-Supervised Learning Method for Spiking Neural Networks Based on Pseudo-Labeling. | Thao N. N. Nguyen, Bharadwaj Veeravalli, Xuanyao Fong |
| 2022 | ISCAS | An FPGA-Based Co-Processor for Spiking Neural Networks with On-Chip STDP-Based Learning. | Thao N. N. Nguyen, Bharadwaj Veeravalli, Xuanyao Fong |
| 2020 | IECON | Aggressive Leakage Current Reduction for Embedded MRAM Using Block-Level Power Gating. | Anh Tuan Do, Xuanyao Fong, Fei Li |
| 2018 | IJCNN | Domain Wall Motion-based XOR-like Activation Unit With A Programmable Threshold. | Suman Deb, Tarun Vatwani, Anupam Chattopadhyay, Arindam Basu, Xuanyao Fong |
| 2016 | ISCAS | A low-voltage, low power STDP synapse implementation using domain-wall magnets for spiking neural networks. | Govind Narasimman, Subhrajit Roy, Xuanyao Fong, Kaushik Roy, Chip-Hong Chang, Arindam Basu |
| 2015 | DAC | Approximate storage for energy efficient spintronic memories. | Ashish Ranjan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan |
| 2015 | DATE | Device/circuit/architecture co-design of reliable STT-MRAM. | Zoha Pajouhi, Xuanyao Fong, Kaushik Roy |
| 2015 | DATE | Spintastic: <u>spin</u>-based s<u>t</u>och<u>astic</u> logic for energy-efficient computing. | Rangharajan Venkatesan, Swagath Venkataramani, Xuanyao Fong, Kaushik Roy, Anand Raghunathan |
| 2014 | ISCAS | Highly reliable memory-based Physical Unclonable Function using Spin-Transfer Torque MRAM. | Le Zhang, Xuanyao Fong, Chip-Hong Chang, Zhi-Hui Kong, Kaushik Roy |
| 2009 | ASPDAC | A design methodology and device/circuit/architecture compatible simulation framework for low-power magnetic quantum cellular automata systems. | Charles Augustine, Behtash Behin-Aein, Xuanyao Fong, Kaushik Roy |
| 2006 | ISLPED | Analysis of super cut-off transistors for ultralow power digital logic circuits. | Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy |