| 2016 | ISCAS | Scalable rasterizer architecture for 3D graphics system. | Yeong-Kang Lai, Yu-Chieh Chung |
| 2016 | ISCAS | Block based depth map estimation algorithm for 2D-to-3D conversion on FPGA. | Yeong-Kang Lai, Chu-Yin Ho, Benjamin Freiling, Thomas Schumann |
| 2015 | ISCAS | An efficient and high quality rasterization algorithm and architecture in 3D graphics systems. | Yeong-Kang Lai, Yu-Chieh Chung |
| 2013 | ISCAS | Hardware implementation for real-time 3D rendering in 2D-to-3D conversion. | Yeong-Kang Lai, Yu-Chieh Chung, Yu-Fan Lai |
| 2012 | ISCAS | High-quality view synthesis algorithm and architecture for 2D to 3D conversion. | Yeong-Kang Lai, Yu-Fan Lai, Jung-Wei Lin |
| 2009 | ICASSP | Model-based early termination scheme for H.264/AVC inter prediction. | Lien-Fei Chen, Shin-Ping Yang, Yeong-Kang Lai |
| 2009 | ISCAS | Hardware Efficient Coarse-to-fine Fast Algorithm for H.264/AVC Variable Block Size Motion Estimation. | Lien-Fei Chen, Shien-Yu Huang, Chi-Yao Liao, Yeong-Kang Lai |
| 2008 | ISCAS | A high-speed 2-D transform architecture with unique kernel for multi-standard video applications. | Chong-Yu Huang, Lien-Fei Chen, Yeong-Kang Lai |
| 2006 | ICASSP | Analysis and Architecture Design for Memory Efficient Parallel Embedded Block Coding Architecture in JPEG 2000. | Lien-Fei Chen, Tai-Lun Huang, Tzau-Min Chou, Yeong-Kang Lai |
| 2005 | ICASSP | Memory analysis and throughput enhancement for cost effective bit-plane coder in JPEG2000 applications. | Lien-Fei Chen, Tai-Lun Huang, Yeong-Kang Lai |
| 2005 | ISCAS | A simple and cost effective video encoder with memory-reducing CAVLC. | Yeong-Kang Lai, Chih-Chung Chou, Yu-Chieh Chung |
| 2005 | ISCAS | A two-way SIMD-based reconfigurable computing architecture for multimedia applications. | Yeong-Kang Lai, Lien-Fei Chen, Jian-Chou Chen, Chun-Wei Chiu |
| 2004 | ISCAS | VLSI architecture of the reconfigurable computing engine for digital signal processing applications. | Lien-Fei Chen, Yeong-Kang Lai |
| 2004 | ISCAS | A performance-driven configurable motion estimator for full-search block-matching algorithm. | Yeong-Kang Lai, Lien-Fei Chen |
| 2004 | ISCAS | A novel memoryless AES cipher architecture for networking applications. | Yeong-Kang Lai, Li-Chung Chang, Lien-Fei Chen, Chih-Chung Chou, Chun-Wei Chiu |
| 2003 | ISCAS | A high data-reuse architecture with double-slice processing for full-search block-matching algorithm. | Yeong-Kang Lai, Lien-Fei Chen |
| 2003 | ISCAS | A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath. | Yeong-Kang Lai, Han-Jen Hsu |
| 2001 | ISCAS | VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. | Yeong-Kang Lai, Yu-Chuan Shu |
| 2000 | ISCAS | A novel VLSI architecture for Lempel-Ziv based data compression. | Yeong-Kang Lai, Kuo-Chen Chen |
| 1997 | ICIP | A Flexible High-Throughput VLSI Architecture with 2-D Data-Reuse for Full-Search Motion Estimation. | Yeong-Kang Lai, Liang-Gee Chen, Tsung-Han Tsai, Po-Cheng Wu |
| 1996 | ICIP | Design strategy for three-dimensional subband filter banks. | Po-Cheng Wu, Liang-Gee Chen, Yeong-Kang Lai, Tsung-Han Tsai |