Yi-Chung Wu
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
4
Venues
2
Active years
2017–2026
Best venue rank
C
Where they publish
Papers
4 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | FCCM | Reconfigurable Computing Challenge: A High-Throughput FPGA Accelerator for Real-Time 3D Gaussian Splatting. | Guan-Wei Lai, Yi-Chen Hu, Chia-Yu Kuo, Wei-Chien Cheng, Yi-Chung Wu |
| 2026 | ISCAS | A 16-nm 24.8 Mbps/mJ Utilization-Aware Dynamic Allocation Read Mapping Accelerator for Next-Generation Sequencing. | Chia-Yu Kuo, Wei-Chien Cheng, Yi-Chung Wu |
| 2025 | ISCAS | A 40-nm 6.75 TOPS/W Quantization-Aware NN Processor for High-Energy-Efficiency Image Recognition. | Jun-Wei Yu, Jen-Chieh Cheng, Jia-You Yu, Shih-Yu Pan, Yi-Chung Wu |
| 2017 | ISCAS | Integration of energy-recycling logic and wireless power transfer for ultra-low-power implantables. | Hsin-Tzu Lin, Yi-Chung Wu, Ping-Hsuan Hsieh, Chia-Hsiang Yang |