| 2025 | DATE | Filter-Based Adaptive Model Pruning for Efficient Incremental Learning on Edge Devices. | Jing-Jia Hung, Yi-Jung Chen, Hsiang-Yun Cheng, Hsu Kao, Chia-Lin Yang |
| 2023 | HPCA | Tensor Movement Orchestration in Multi-GPU Training Systems. | Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang |
| 2022 | ASPDAC | PUMP: Profiling-free Unified Memory Prefetcher for Large DNN Model Support. | Chung-Hsiang Lin, Shao-Fu Lin, Yi-Jung Chen, En-Yu Jenp, Chia-Lin Yang |
| 2020 | SAC | Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. | Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama |
| 2014 | DATE | Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs. | Meng-Ling Tsai, Yi-Jung Chen, Yi-Ting Chen, Ru-Hua Chang |
| 2013 | ISLPED | Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs. | Ping-Sheng Lin, Yi-Jung Chen, Chia-Lin Yang, Yi-Chang Lu |
| 2012 | ICCAD | Distributed memory interface synthesis for Network-on-Chips with 3D-stacked DRAMs. | Yi-Jung Chen, Chia-Lin Yang, Jian-Jia Chen |
| 2012 | ICCD | SECRET: Selective error correction for refresh energy reduction in DRAMs. | Chung-Hsiang Lin, De-Yu Shen, Yi-Jung Chen, Chia-Lin Yang, Cheng-Yuan Michael Wang |
| 2010 | DATE | PM-COSYN: PE and memory co-synthesis for MPSoCs. | Yi-Jung Chen, Chia-Lin Yang, Po-Han Wang |
| 2007 | CASES | Cache leakage control mechanism for hard real-time systems. | Jaw-Wei Chi, Chia-Lin Yang, Yi-Jung Chen, Jian-Jia Chen |
| 2007 | SAC | An architectural co-synthesis algorithm for energy-aware network-on-chip design. | Wei-Hsuan Hung, Yi-Jung Chen, Chia-Lin Yang, Yen-Sheng Chang, Alan P. Su |