| 2012 | DAC | Efficient trimmed-sample Monte Carlo methodology and yield-aware design flow for analog circuits. | Chin-Cheng Kuo, Wei-Yi Hu, Yi-Hung Chen, Jui-Feng Kuan, Yi-Kan Cheng |
| 2012 | ICCAD | Configurable analog routing methodology via technology and design constraint unification. | Po-Cheng Pan, Hung-Ming Chen, Yi-Kan Cheng, Jill Liu, Wei-Yi Hu |
| 2000 | ICCD | Application-Based, Transistor-Level Full-Chip Power Analysis for 700 MHz PowerPC | Yi-Kan Cheng, David Bearden, Kanti Suryadevara |
| 1999 | ICCAD | An efficient method for hot-spot identification in ULSI circuits. | Yi-Kan Cheng, Sung-Mo Kang |
| 1999 | ISCAS | Temperature-driven power and timing analysis for CMOS ULSI circuits. | Yi-Kan Cheng, Sung-Mo Kang |
| 1996 | DAC | iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. | Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang |
| 1996 | DAC | Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. | Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang |
| 1996 | DATE | ETS-A: A New Electrothermal Simulator for CMOS VLSI Circuits. | Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang |
| 1995 | ISCAS | Chip-Level Thermal Simulator to Predict VLSI Chip Temperature. | Yi-Kan Cheng, Sung-Mo Kang |