| 2025 | DAC | Power-Grid Structure Exploration with Unified Sequence-based Learning Framework. | Yi-Lin Chuang, Hao-Wei Chan, Chih-Yun Yen, Shih-An Hsieh, Ching-Feng Chen, Sheng-Te Lai |
| 2020 | CHI | Exploring the Design Space of User-System Communication for Smart-home Routine Assistants. | Yi-Shyuan Chiang, Ruei-Che Chang, Yi-Lin Chuang, Shih-Ya Chou, Hao-Ping Lee, I-Ju Lin, Jian-Hua Jiang Chen, Yung-Ju Chang |
| 2012 | DATE | Statistical thermal modeling and optimization considering leakage power variations. | Da-Cheng Juan, Yi-Lin Chuang, Diana Marculescu, Yao-Wen Chang |
| 2011 | ICCAD | PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs. | Yi-Lin Chuang, Hong-Ting Lin, Tsung-Yi Ho, Yao-Wen Chang, Diana Marculescu |
| 2011 | ISLPED | Pulsed-latch-based clock tree migration for dynamic power reduction. | Hong-Ting Lin, Yi-Lin Chuang, Tsung-Yi Ho |
| 2010 | DAC | Pulsed-latch aware placement for timing-integrity optimization. | Yi-Lin Chuang, Sangmin Kim, Youngsoo Shin, Yao-Wen Chang |
| 2010 | ICCAD | Design-hierarchy aware mixed-size placement for routability optimization. | Yi-Lin Chuang, Gi-Joon Nam, Charles J. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan |
| 2009 | ICCAD | Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs. | Yi-Lin Chuang, Po-Wei Lee, Yao-Wen Chang |
| 2008 | ICCAD | Constraint graph-based macro placement for modern mixed-size circuit designs. | Hsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang |