Yin-Nien Chen
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
2
Active years
2012–2017
Best venue rank
C
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ISCAS | Exploration and evaluation of low-dropout linear voltage regulator with FinFET, TFET and hybrid TFET-FinFET implementations. | Chia-Ning Chang, Yin-Nien Chen, Po-Tsang Huang, Pin Su, Ching-Te Chuang |
| 2015 | ISCAS | Evaluation of TFET and FinFET devices and 32-Bit CLA circuits considering work function variation and line-edge roughness. | Chien-Ju Chen, Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2014 | ISCAS | Investigation and optimization of monolithic 3D logic circuits and SRAM cells considering interlayer coupling. | Ming-Long Fan, Vita Pi-Ho Hu, Yin-Nien Chen, Pin Su, Ching-Te Chuang |
| 2014 | ISLPED | Ultra-low voltage mixed TFET-MOSFET 8T SRAM cell. | Yin-Nien Chen, Ming-Long Fan, Vita Pi-Ho Hu, Pin Su, Ching-Te Chuang |
| 2012 | ISCAS | High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. | Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu |