| 2010 | ICONIP | Array-Enhanced Stochastic Resonance in a Network of Noisy Neuromorphic Circuits. | Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | ASPDAC | A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | ICONIP | Exploiting Temporal Noises and Device Fluctuations in Enhancing Fidelity of Pulse-Density Modulator Consisting of Single-Electron Neural Circuits. | Andrew Kilinga Kikombo, Tetsuya Asai, Yoshihito Amemiya |
| 2009 | IJCNN | A pulse-density modulation circuit exhibiting noise shaping with single-electron neurons. | Andrew Kilinga Kikombo, Tetsuya Asai, Takahide Oya, Alexandre Schmid, Yusuf Leblebici, Yoshihito Amemiya |
| 2009 | ISCAS | On-chip PVT Compensation Techniques for Low-voltage CMOS Digital LSIs. | Yusuke Tsugita, Ken Ueno, Tetsuya Asai, Yoshihito Amemiya, Tetsuya Hirose |
| 2009 | ISCAS | Low-power Clock Reference Circuit for Intermittent Operation of Subthreshold LSIs. | Ken Ueno, Tetsuya Asai, Yoshihito Amemiya |
| 2008 | ICONIP | Noise-Tolerant Analog Circuits for Sensory Segmentation Based on Symmetric STDP Learning. | Gessyca Maria Tovar, Tetsuya Asai, Yoshihito Amemiya |
| 2007 | ICONIP | Analog CMOS Circuits Implementing Neural Segmentation Model Based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | IJCNN | Neuromorphic CMOS Circuits implementing a Novel Neural Segmentation Model based on Symmetric STDP Learning. | Gessyca Maria Tovar, Eric Shun Fukuda, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2007 | ISCAS | Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIs. | Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya |
| 2005 | IJCNN | Analog current-mode CMOS implementation of central pattern generator for robot locomotion. | Kazuki Nakada, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya |
| 2005 | IJCNN | Noise performance of single-electron depressing synapses for neuronal synchrony detection. | Takahide Oya, Tetsuya Asai, Ryo Kagaya, Yoshihito Amemiya |
| 2005 | ISCAS | Analog CMOS implementation of a neuromorphic oscillator with current-mode low-pass filters. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2005 | ISCAS | Single-electron circuit for inhibitory spiking neural network with fault-tolerant architecture. | Takahide Oya, Tetsuya Asai, Yoshihito Amemiya, Alexandre Schmid, Yusuf Leblebici |
| 2004 | IJCNN | A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. | Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya |
| 2004 | ISCAS | An analog CMOS chip implementing a CNN-based locomotion controller for quadruped walking robots. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2003 | IJCNN | An analog neural oscillator circuit for locomotion controller in quadruped walking robot. | Kazuki Nakada, Tetsuya Asai, Yoshihito Amemiya |
| 2002 | SMC | A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. | Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya |
| 2000 | IJCNN | An Analog-Digital Hybrid CMOS Circuit for Two-Dimensional Motion Detection with Correlation Neural Networks. | Tetsuya Asai, Masato Koutani, Yoshihito Amemiya |
| 1998 | KES | nu-MOS cellular-automaton devices for intelligent image sensors. | Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya |