Young-chul Rams Cho
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
1
Active years
2016–2017
Best venue rank
C
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2017 | ISCAS | Fast cycle-accurate compile based simulator for reconfigurable processor. | Narasinga Rao Miniskar, Raj Narayana Gadde, Young-chul Rams Cho, Sukjin Kim |
| 2016 | ISCAS | Intra mode power saving methodology for CGRA-based reconfigurable processor architectures. | Narasinga Rao Miniskar, Rahul R. Patil, Raj Narayana Gadde, Young-chul Rams Cho, Sukjin Kim, Shi Hwa Lee |