| 2023 | DAC | Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs. | Kuan-Cheng Chen, Yan-Lin Chen, Yu-Sheng Lu, Yao-Wen Chang |
| 2022 | DAC | Thermal-aware optical-electrical routing codesign for on-chip signal communications. | Yu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang |
| 2020 | DAC | Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip. | Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang |
| 2020 | DAC | A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing. | Yu-Sheng Lu, Sheng-Jung Yu, Yao-Wen Chang |
| 2018 | DAC | WB-trees: a meshed tree representation for FinFET analog layout designs. | Yu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang |
| 2016 | DAC | Timing-driven cell placement optimization for early slack histogram compression. | Chau-Chin Huang, Yen-Chun Liu, Yu-Sheng Lu, Yun-Chih Kuo, Yao-Wen Chang, Sy-Yen Kuo |
| 2012 | INDIN | Experimental evaluation of disturbance estimation algorithms for servo control systems. | Yu-Sheng Lu, Chang-Yong Syu |
| 2008 | DAC | Type-matching clock tree for zero skew clock gating. | Chia-Ming Chang, Shih-Hsu Huang, Yuan-Kai Ho, Jia-Zong Lin, Hsin-Po Wang, Yu-Sheng Lu |