Yuhsiang M. Tsai
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
3
Venues
1
Active years
2020–2021
Best venue rank
B
Where they publish
Papers
3 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2021 | EuroPar | Porting Sparse Linear Algebra to Intel GPUs. | Yuhsiang M. Tsai, Terry Cojean, Hartwig Anzt |
| 2020 | EuroPar | Balanced and Compressed Coordinate Layout for the Sparse Matrix-Vector Product on GPUs. | Jos Ignacio Aliaga, Hartwig Anzt, Enrique S. Quintana-Ort, Andrs E. Toms, Yuhsiang M. Tsai |
| 2020 | EuroPar | Preparing Ginkgo for AMD GPUs - A Testimonial on Porting CUDA Code to HIP. | Yuhsiang M. Tsai, Terry Cojean, Tobias Ribizel, Hartwig Anzt |