| 2026 | ACL | FastKV: Decoupling of Context Reduction and KV Cache Compression for Prefill-Decoding Acceleration. | Dongwon Jo, Jiwon Song, Yulhwa Kim, Jae-Joon Kim |
| 2026 | DATE | 3D Integration of Hybrid IGZO/Si and IGZO eDRAMs for High-Density/High-Performance On-Chip Memory. | Munhyeon Kim, Sukhyun Choi, Yulhwa Kim, Jae-Joon Kim |
| 2025 | ACL | L4Q: Parameter Efficient Quantization-Aware Fine-Tuning on Large Language Models. | Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim |
| 2025 | DATE | Column-wise Quantization of Weights and Partial Sums for Accurate and Efficient Compute-In-Memory Accelerators. | Jiyoon Kim, Kang Eun Jeon, Yulhwa Kim, Jong Hwan Ko |
| 2025 | DATE | Compute-in-Memory Array Design Using Stacked Hybrid IGZO/Si eDRAM cells. | Munhyeon Kim, Yulhwa Kim, Jae-Joon Kim |
| 2024 | HPCA | FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. | Jaeyong Jang, Yulhwa Kim, Juheun Lee, Jae-Joon Kim |
| 2024 | ICML | SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. | Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim |
| 2023 | ICLR | Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. | Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon Kim |
| 2021 | DATE | Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. | Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim |
| 2020 | DAC | Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. | Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim |
| 2020 | ISLPED | Time-step interleaved weight reuse for LSTM neural network computing. | Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim |
| 2019 | ASPDAC | In-memory batch-normalization for resistive memory based binary neural network hardware. | Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim |
| 2019 | DATE | Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. | Wooseok Yi, Yulhwa Kim, Jae-Joon Kim |
| 2018 | ISLPED | Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. | Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim |
| 2018 | ISLPED | Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. | Jinseok Kim, Yulhwa Kim, Sungho Kim, Jae-Joon Kim |