Yung-Hui Chung
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
7
Venues
1
Active years
2013–2025
Best venue rank
C
Where they publish
Papers
7 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2025 | ISCAS | A 12-bit SAR ADC Utilizing Background Capacitor Calibration with LLM-LMS Algorithm. | Chung-Wei Lin, Yung-Hui Chung |
| 2024 | ISCAS | A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS. | Wei-Chung Lin, Yung-Chi Chang, Yung-Hui Chung |
| 2024 | ISCAS | A 105-dB SFDR 16-bit SAR ADC with a Window Capacitor Calibration Scheme. | Qi-Fen Zeng, Chia-Hui Tien, Yung-Hui Chung |
| 2019 | ISCAS | A 12-Bit Synchronous-SAR ADC for IoT Applications. | Yung-Hui Chung, Min-Sheng Chiang |
| 2016 | ISCAS | A PVT-tracking metastability detector for asynchronous ADCs. | Yung-Hui Chung, Chia-Wei Yen |
| 2014 | ISCAS | Perturbation-based digital background calibration technique for pipelined ADCs. | Yung-Hui Chung |
| 2013 | ISCAS | The swapping binary-window DAC switching technique for SAR ADCs. | Yung-Hui Chung |