Yusuke Kanazawa
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
2
Venues
2
Active years
2002–2004
Best venue rank
B
Where they publish
Papers
2 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2004 | IJCNN | A MOS circuit for depressing synapse and its application to contrast-invariant pattern classification and synchrony detection. | Tetsuya Asai, Yusuke Kanazawa, Tetsuya Hirose, Yoshihito Amemiya |
| 2002 | SMC | A novel architecture for implementing large-scale Hopfield neural networks using CDMA communication technology. | Yusuke Kanazawa, Takashi Yamada, Tetsuya Asai, Yoshihito Amemiya |