Yuxiang Huan
Publication record assembled from the DBLP archive of ranked conferences.
Papers indexed
5
Venues
3
Active years
2016–2026
Best venue rank
A*
Where they publish
Papers
5 indexed papers, newest first.
| Year | Venue | Title | Authors |
|---|---|---|---|
| 2026 | ISCA | WaferBRAIN: Whole-Brain Scale Neuromorphic Architecture Based on Wafer-Scale Integration. | Yukun Feng, Hao Jia, Liangyu Gan, Haoming Chu, Yufan He, Jiaxin Yin, Lirong Zheng, Ning Ma, Yuxiang Huan |
| 2020 | VTC | An Autonomous Error-Tolerant Architecture Featuring Self-reparation for Convolutional Neural Networks. | Lizheng Liu, Yuxiang Huan, Zhuo Zou, Xiaoming Hu, Lirong Zheng |
| 2018 | ISCAS | A 3D Tiled Low Power Accelerator for Convolutional Neural Network. | Yuxiang Huan, Jiawei Xu, Lirong Zheng, Hannu Tenhunen, Zhuo Zou |
| 2018 | ISCAS | TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design. | Yi Jin, Yuxiang Huan, Haoming Chu, Zhuo Zou, Lirong Zheng |
| 2016 | ISCAS | A 101.4 GOPS/W reconfigurable and scalable control-centric embedded processor for domain-specific applications. | Ning Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng, Yuxiang Huan, Stefan Blixt |