| 2017 | ASPDAC | BHNN: A memory-efficient accelerator for compressing deep neural networks with blocked hashing techniques. | Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui |
| 2017 | DSAA | M3A: Model, MetaModel and Anomaly Detection for Inter-arrivals of Web Searches and Postings. | Da-Cheng Juan, Neil Shah, Mingyu Tang, Zhiliang Qian, Diana Marculescu, Christos Faloutsos |
| 2016 | ASPDAC | LRADNN: High-throughput and energy-efficient Deep Neural Network accelerator using Low Rank Approximation. | Jingyang Zhu, Zhiliang Qian, Chi-Ying Tsui |
| 2014 | ASPDAC | A comprehensive and accurate latency model for Network-on-Chip performance analysis. | Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu |
| 2014 | DAC | Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis. | Yuankun Xue, Zhiliang Qian, Paul Bogdan, Fan Ye, Chi-Ying Tsui |
| 2013 | DATE | SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model. | Zhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu |
| 2013 | ICCAD | Performance evaluation of multicore systems: from traffic analysis to latency predictions (embedded tutorial). | Zhiliang Qian, Paul Bogdan, Chi-Ying Tsui, Radu Marculescu |
| 2012 | DATE | A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels. | Zhiliang Qian, Ying Fei Teh, Chi-Ying Tsui |
| 2011 | ASPDAC | A thermal-aware application specific routing algorithm for Network-on-Chip design. | Zhiliang Qian, Chi-Ying Tsui |