A 1.5 Ghz VLIW DSP CPU with Integrated Floating Point and Fixed Point Instructions in 40 nm CMOS.
Timothy Anderson, Duc Bui, Shriram Moharil, Soujanya Narnur, Mujibur Rahman, Anthony Lell, Eric Biscondi, Ashish Shrivastava, Peter Dent, Mingjian Yan, Hasan Mahmood
VenueCARITH
Year2011
ProceedingsIEEE Symposium on Computer Arithmetic
DBLP recordconf/arith/AndersonBMNRLBSDYM10 ↗
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