Skip to content
cs-conference-ranking
.org
By subfield
By rank
Methodology
⌕
Search 971 venues
Home
/
DATE
/
Paper
Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective.
Pavel Ghosh
,
Arunabha Sen
Venue
A
DATE
Year
2010
Proceedings
DATE
DBLP record
conf/date/GhoshS10 ↗
Browse the full
DATE paper archive
.