Virtual Testing Environment for A/D Converters in Verilog-A and Maple Platform.
Ondrej Subrt, Petr Struhovsk, Pravoslav Martnek, Jir Hospodka
Browse the full DDECS paper archive.
Ondrej Subrt, Petr Struhovsk, Pravoslav Martnek, Jir Hospodka
Browse the full DDECS paper archive.