Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit.
Bibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar
Browse the full DSD paper archive.
Bibhash Sen, Anik Sengupta, Mamata Dalui, Biplab K. Sikdar
Browse the full DSD paper archive.