Design and Verification for Hierarchical Power Efficiency System (HPES) Design Techniques Using Low Power CMOS Digital Logic.
Taikyeong T. Jeong, Jaemyoung Lee
VenueMulticonferenceICCS
Year2006
ProceedingsInternational Conference on Computational Science (1)
DBLP recordconf/iccS/JeongL06 ↗
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