FPGA Implementation of a Pseudo-Random Signal Generator for RF Hardware Test and Evaluation.
Randeep S. Baweja, Devin B. Ridge, Harpreet S. Dhillon, William C. Headley
Browse the full IPCCC paper archive.
Randeep S. Baweja, Devin B. Ridge, Harpreet S. Dhillon, William C. Headley
Browse the full IPCCC paper archive.