Skip to content

A 10-b 100-MS/s pipelined ADC with an optimized bit-stage resolution in 65nm CMOS technology.

Pasquale Delizia, Gianni Saccomanno, Stefano D'Amico, Andrea Baschirotto

VenueCISCAS
Year2010
ProceedingsISCAS

Browse the full ISCAS paper archive.