A 100 MHz 9.14-mW 8-Bit Shift Register Using Double-Edge Triggered Flip-Flop.
Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang
Browse the full ISCAS paper archive.
Uday Kiran Naidu Ekkurthi, Venkatesh Dasari, Jyoshnavi Akiri, Chua-Chin Wang
Browse the full ISCAS paper archive.