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Paper
A clock recovery circuit using half-rate 4-oversampling PD.
Hyung-Wook Jang
,
Sung-Sop Lee
,
Jin-Ku Kang
Venue
C
ISCAS
Year
2005
Proceedings
ISCAS (3)
DBLP record
conf/iscas/JangLK05 ↗
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