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Paper
A 12-bit, 2.5-bit/cycle, 1 MS/s two-stage cyclic ADC, for high-speed CMOS Image sensors.
Amandeep Kaur
,
Deepak Mishra
,
Mukul Sarkar
Venue
C
ISCAS
Year
2018
Proceedings
ISCAS
DBLP record
conf/iscas/Kaur0S18 ↗
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