A 1.2 - 6.4 GHz clock generator with a low-power DCO and programmable multiplier in 40-nm CMOS.
Tero Tikka, Kari Stadius, Jussi Ryynnen, Martti Voutilainen
Browse the full ISCAS paper archive.
Tero Tikka, Kari Stadius, Jussi Ryynnen, Martti Voutilainen
Browse the full ISCAS paper archive.