A monolithic 1.25 Gbits/sec CMOS clock/data recovery circuit for fibre channel transceiver.
L. Wu, Huiting Chen, S. Nagavarapu, Randall L. Geiger, Edward Lee, W. Black
Browse the full ISCAS paper archive.
L. Wu, Huiting Chen, S. Nagavarapu, Randall L. Geiger, Edward Lee, W. Black
Browse the full ISCAS paper archive.