Design and Analysis of a Family of pW-Level Sub-1V CMOS VRGs by Stacking a Current-Source Transistor and a Resistive-Load Transistor.
Tong Zhang, Dingguo Zhang, Jing Jin, Patrick P. Mercier, Hui Wang
Browse the full ISCAS paper archive.
Tong Zhang, Dingguo Zhang, Jing Jin, Patrick P. Mercier, Hui Wang
Browse the full ISCAS paper archive.