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Paper
FPGA design of a truncated SVD based receiver for the detection of SEFDM signals.
Ryan C. Grammenos
,
Safa Isam
,
Izzat Darwazeh
Venue
B
PIMRC
Year
2011
Proceedings
PIMRC
DBLP record
conf/pimrc/GrammenosID11 ↗
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