| 2026 | DDECS | Measurement-Driven Adaptive Low-Overhead Implementation of Multi-Controlled Toffoli Gates. | Abhoy Kole, Till Schnittka, Rolf Drechsler |
| 2026 | DDECS | Fan-In Aware Graph-Based Optimization for MAC-Based in-Memory Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | DDECS | Towards an Automated Debugging Approach for Fault Identification in Quantum Circuits. | Anton Maidl, Abhoy Kole, Kamalika Datta, Jannis Stoppe, Rolf Drechsler |
| 2025 | DSD | A Comprehensive Synthesis and Verification Approach for RRAM-Based Neuromorphic Computing. | Fatemeh Shirinzadeh, Abhoy Kole, Kamalika Datta, Saeideh Shirinzadeh, Rolf Drechsler |
| 2025 | FDL | System-Level Design Space Exploration for Matrix Multiplication using Compute-In-Memory Unit. | Deepak Ravibabu, Sallar Ahmadi-Pour, Muhammad Hassan, Abhoy Kole, Chandan Kumar Jha, Rolf Drechsler |
| 2024 | DATE | Dynamic Realization of Multiple Control Toffoli Gate. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2024 | DATE | Complete and Efficient Verification for a RISC-V Processor Using Formal Verification. | Lennart Weingarten, Kamalika Datta, Abhoy Kole, Rolf Drechsler |
| 2024 | RC | Is Simulation the only Alternative for Effective Verification of Dynamic Quantum Circuits? | Liam Hurwitz, Kamalika Datta, Abhoy Kole, Rolf Drechsler |
| 2024 | VLSID | In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. | Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler |
| 2023 | DATE | Extending the Design Space of Dynamic Quantum Circuits for Toffoli based Network. | Abhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler |
| 2023 | RC | Improved Cost-Metric for Nearest Neighbor Mapping of Quantum Circuits to 2-Dimensional Hexagonal Architecture. | Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler |
| 2023 | RC | Exploiting the Benefits of Clean Ancilla Based Toffoli Gate Decomposition Across Architectures. | Abhoy Kole, Kamalika Datta, Philipp Niemann, Indranil Sengupta, Rolf Drechsler |
| 2022 | DSD | SAT-based Exact Synthesis of Ternary Reversible Circuits using a Functionally Complete Gate Library. | Abhoy Kole, Kamalika Datta, Indranil Sengupta, Rolf Drechsler |
| 2022 | GI | Mapping Quantum Circuits to 2-Dimensional Quantum Architectures. | Kamalika Datta, Abhoy Kole, Indranil Sengupta, Rolf Drechsler |
| 2017 | RC | Test Pattern Generation Effort Evaluation of Reversible Circuits. | Abhoy Kole, Robert Wille, Kamalika Datta, Indranil Sengupta |
| 2017 | RC | Design of Efficient Quantum Circuits Using Nearest Neighbor Constraint in 2D Architecture. | Leniency Marbaniang, Abhoy Kole, Kamalika Datta, Indranil Sengupta |
| 2017 | RC | Improved Decomposition of Multiple-Control Ternary Toffoli Gates Using Muthukrishnan-Stroud Quantum Gates. | P. Mercy Nesa Rani, Abhoy Kole, Kamalika Datta, Indranil Sengupta |
| 2017 | VLSID | Improved NCV Gate Realization of Arbitrary Size Toffoli Gates. | Abhoy Kole, Kamalika Datta |
| 2015 | RC | Towards a Cost Metric for Nearest Neighbor Constraints in Reversible Circuits. | Abhoy Kole, Kamalika Datta, Indranil Sengupta, Robert Wille |