| 2026 | IncepLite: An FPGA Based InceptionNet Accelerator for ECG Classification at Edge Devices. | Anju Yajjala, Muralidhar Pullakandam, Gopala Krishna Thota |
| 2026 | Energy Efficient Spiking Neural Networks for Temporal Patterns Using EvoSNN-MO. | Murali Krishna Yadav, B. Naresh Kumar Reddy, Yellapragada Charan Krishna, Talluri Vineel Jessy |
| 2026 | Thermal Runaway Analysis of Analog PIM Accelerators. | Huatao Wu, Sandip Kundu |
| 2026 | An FPGA-Based Secure and Privacy-Aware RISC-V SoC with a CNN Accelerator for Edge AI. | Priyanshu Tyagi, Rhythm Patel, Sparsh Mittal, Rekha Singhal |
| 2026 | A 98.5- TOPS/W and 0.73-TOPS/mm | Priyanshu Tyagi, Aayush Gautam, Sparsh Mittal |
| 2026 | Machine Dynamics-Aware CPS Scheduling and Iterative Validation for Industry 4.0. | Pietro Turco, Enrico Fraccaroli, Samarjit Chakraborty, Franco Fummi |
| 2026 | DP-VSA: DSP Packing-Based Vector Systolic Accelerator with Dual Precision Support on FPGAs. | Aashish Kumar Tiwary, Yathin Kumar Attuluri, Nanditha Rao |
| 2026 | Hardware Trojan Detection and Interpretation Using Graph Neural Networks. | Jayanth Thangellamudi, Negar Etemadyrad, Liang Zhao, Sai Manoj P. D. |
| 2026 | A Transistor-Level Implementation of Radix-2 and Radix-4 FFT Using Logical Effort. | Harsh Raj Thakur, Sparsh Mittal |
| 2026 | Design and FPGA Implementation of a Wide-Range and Area-Efficient Programmable Frequency Divider. | Shriniket Hemant Tare, Rohit Chaurasiya, Dron Sankhala, Chandan Yadav |
| 2026 | Adaptive Control Strategies in DC-DC Converter for Improved Transient Response and Efficiency for High Load Slew and Fast Switching Loops. | Bharadwaj Subramaniam, Zia Abbas |
| 2026 | Leveraging XAI for Semiconductor Electrical - Parameter Characterization Using Machine Learning. | Siddhi Srivastava, Debojyoti Roy, Hriddhi Srivastava, Khushwant Sehra, Manoj Saxena |
| 2026 | A 146 GOPS and 7.2 TOPS/W 6T SRAM-Based Analog CIM Macro Using Bit-Splitting for 8-Bit MAC Operations. | Cheena Singhal, Abhishek Goel, Sparsh Mittal, Sudeb Dasgupta |
| 2026 | LInC-BMC: A Lookahead Informed Clause Deletion Mechanism for Bounded Model Checking. | Satyam Shubham, Sutirtha Bhattacharyya, Ansuman Banerjee, Raj Kumar Gajavelly |
| 2026 | Post-Quantum HAWK Signature Acceleration with RISC-V-Based Hardware-Software Co-Design. | Rishabh Shrivastava, Utsav Banerjee |
| 2026 | A Novel VLSI Architecture and FPGA Implementation of Hardware-Efficient Mfocuss-Based Wideband Spectrum Sensor for Dynamic Spectrum Access. | Aayush Shrivas, Rahul Shrestha |
| 2026 | A Unified BIST Framework for High-Coverage Fault Detection with Area and Power Minimization. | Athira J. Shenoy, Adersh V. R, Nikhil M |
| 2026 | A Low Power 8-bit 3GS/s Current Steering DAC at 1.2V Supply Achieving >49 dB SFDR in 65nm CMOS. | Anamika Sharma, Rajesh Zele |
| 2026 | Exploring Bit-Flip Attacks on DQNs with a Hash-Driven Defense Accelerator. | Om Chandra Sharma, Anmol Yadav, Vihan Sachin Karnik, Palash Das |
| 2026 | PRISM: Photonic Reconfigurable In-Situ Memory for Next-Gen AI Workloads. | Pratham Sharma, Santosh Kumar Vishvakarma |
| 2026 | A Partially Loop-Unrolled Noise-Shaping SAR ADC Achieving 57dB-SNDR in 40MHz-BW at 320MS/s in 18nm FD-SOI CMOS Technology. | Anamika Sharma, Luv Pandey, Paras Garg, Rajesh Zele |
| 2026 | Flash-Based Dynamic Dot Product Acceleration. | Kyler R. Scott, Sunil P. Khatri |
| 2026 | A 2.95 pJ/b 42Gb/s PAM-8 Clock and Data Recovery. | Saurabh Saxena, Neel Hingrajiya, Suryadipto Mukherjee, Vivek Pala |
| 2026 | A 8-16 Gb/s/pin Full-Duplex Voltage-Mode Transmitter with Pulse Width Modulation Based Equalization and Analog Echo Canceller. | Saurabh Saxena, Vinod Ganesan, Shubham Choudhary |
| 2026 | RTL Information Tracker and its Applications in Quantifying the Security Impact of HLS Optimizations. | Nilotpola Sarma, Sunny Priyadarshi, Chandan Karfa |