| 2024 | ITC | Unsupervised Learning Provides Intelligence for Testing Hard to Detect Faults. | Soham Roy, Vishwani D. Agrawal |
| 2024 | VLSID | An Amalgamated Testability Measure Derived from Machine Intelligence. | Soham Roy, Vishwani D. Agrawal |
| 2022 | VTS | Fault Modeling and Test Generation for Technology-Specific Defects of Skyrmion Logic Circuits. | Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal |
| 2021 | ETS | Unsupervised Learning in Test Generation for Digital Integrated Circuits. | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
| 2021 | VLSID | Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
| 2021 | VTS | Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
| 2021 | VTS | Defect Characterization and Testing of Skyrmion-Based Logic Circuits. | Ziqi Zhou, Ujjwal Guin, Peng Li, Vishwani D. Agrawal |
| 2020 | ITC | Machine Intelligence for Efficient Test Pattern Generation. | Soham Roy, Spencer K. Millican, Vishwani D. Agrawal |
| 2020 | VLSID | Message from the Steering Committee Chair. | Vishwani D. Agrawal |
| 2020 | VTS | Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. | Yang Sun, Spencer K. Millican, Vishwani D. Agrawal |
| 2019 | VLSID | Two-Pattern ∆IDDQ Test for Recycled IC Detection. | Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal |
| 2019 | VLSID | Energy Efficient Power Distribution on Many-Core SoC. | Mustafa M. Shihab, Vishwani D. Agrawal |
| 2019 | VTS | Special Session: Delay Fault Testing - Present and Future. | Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal |
| 2018 | VTS | Modeling and test generation for combinational hardware Trojans. | Ziqi Zhou, Ujjwal Guin, Vishwani D. Agrawal |
| 2016 | VLSID | Database Search and ATPG - Interdisciplinary Domains and Algorithms. | Muralidharan Venkatasubramanian, Vishwani D. Agrawal |
| 2015 | VLSID | Few Good Frequencies for Power-Constrained Test. | Sindhu Gunasekar, Vishwani D. Agrawal |
| 2015 | VLSID | Diagnostic Tests for Pre-bond TSV Defects. | Bei Zhang, Vishwani D. Agrawal |
| 2014 | ICCD | An optimized diagnostic procedure for pre-bond TSV defects. | Bei Zhang, Vishwani D. Agrawal |
| 2013 | ITC | High sensitivity test signatures for unconventional analog circuit test paradigms. | Suraj Sindia, Vishwani D. Agrawal |
| 2013 | ITC | ATE test time reduction using asynchronous clock period. | Praveen Venkataramani, Vishwani D. Agrawal |
| 2013 | VLSID | Optimum Test Schedule for SoC with Specified Clock Frequencies and Supply Voltages. | Vijay Sheshadri, Vishwani D. Agrawal, Prathima Agrawal |
| 2013 | VLSID | Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage. | Praveen Venkataramani, Vishwani D. Agrawal |
| 2013 | VTS | Finding best voltage and frequency to shorten power-constrained test time. | Praveen Venkataramani, Suraj Sindia, Vishwani D. Agrawal |
| 2012 | ISCAS | Impact of process variations on computers used for image processing. | Suraj Sindia, Fa Foster Dai, Vishwani D. Agrawal, Virendra Singh |
| 2012 | VLSID | Keynote Talk: A History of the VLSI Design Conference. | Vishwani D. Agrawal |
| 2012 | VLSID | Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
| 2012 | VTS | Towards spatial fault resilience in array processors. | Suraj Sindia, Vishwani D. Agrawal |
| 2012 | VTS | Net diagnosis using stuck-at and transition fault models. | Lixing Zhao, Vishwani D. Agrawal |
| 2011 | ICCD | Reduced complexity test generation algorithms for transition fault diagnosis. | Yu Zhang, Vishwani D. Agrawal |
| 2011 | VLSID | True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. | Kyungseok Kim, Vishwani D. Agrawal |
| 2011 | VTS | An efficient test data reduction technique through dynamic pattern mixing across multiple fault models. | Srinivasulu Alampally, R. T. Venkatesh, Priyadharshini Shanmugasundaram, Rubin A. Parekhji, Vishwani D. Agrawal |
| 2011 | VTS | Dynamic scan clock control for test time reduction maintaining peak power limit. | Priyadharshini Shanmugasundaram, Vishwani D. Agrawal |
| 2011 | VTS | Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. | Suraj Sindia, Vishwani D. Agrawal, Virendra Singh |
| 2010 | ETS | A diagnostic test generation system and a coverage metric. | Yu Zhang, Vishwani D. Agrawal |
| 2010 | ITC | A diagnostic test generation system. | Yu Zhang, Vishwani D. Agrawal |
| 2010 | VLSID | Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. | Suraj Sindia, Virendra Singh, Vishwani D. Agrawal |
| 2010 | VTS | Application of signal and noise theory to digital VLSI testing. | Nitin Yogi, Vishwani D. Agrawal |
| 2009 | ETS | A Two Phase Approach for Minimal Diagnostic Test Set Generation. | Mohammed Ashfaq Shukoor, Vishwani D. Agrawal |
| 2009 | ETS | On Minimization of Peak Power for Scan Circuit during Test. | Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal |
| 2009 | ISCAS | Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. | Wei Jiang, Vishwani D. Agrawal |
| 2009 | VLSID | Soft Error Rates with Inertial and Logical Masking. | Fan Wang, Vishwani D. Agrawal |
| 2009 | VTS | Output Hazard-Free Transition Delay Fault Test Generation. | Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal |
| 2008 | ISLPED | A tutorial on test power. | Vishwani D. Agrawal |
| 2008 | ITC | Built-in Self-Calibration of On-chip DAC and ADC. | Wei Jiang, Vishwani D. Agrawal |
| 2008 | VLSID | Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. | Yuanlin Lu, Vishwani D. Agrawal |
| 2008 | VLSID | Single Event Upset: An Embedded Tutorial. | Fan Wang, Vishwani D. Agrawal |
| 2008 | VTS | Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. | Rajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal |
| 2007 | ITC | Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. | Soumitra Bose, Vishwani D. Agrawal |
| 2007 | ITC | Delay fault simulation with bounded gate delay mode. | Soumitra Bose, Hillary Grimes, Vishwani D. Agrawal |
| 2007 | ITC | SPARTAN: a spectral and information theoretic approach to partial-scan. | Omar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal |
| 2007 | VLSID | A Reduced Complexity Algorithm for Minimizing N-Detect Tests. | Kalyana R. Kantipudi, Vishwani D. Agrawal |
| 2007 | VLSID | Statistical Leakage and Timing Optimization for Submicron Process Variation. | Yuanlin Lu, Vishwani D. Agrawal |
| 2007 | VLSID | Spectral RTL Test Generation for Microprocessors. | Nitin Yogi, Vishwani D. Agrawal |
| 2007 | VTS | Delay Test Quality Evaluation Using Bounded Gate Delays. | Soumitra Bose, Vishwani D. Agrawal |
| 2006 | ISLPED | Input-specific dynamic power optimization for VLSI circuits. | Fei Hu, Vishwani D. Agrawal |
| 2006 | ITC | Fault Coverage Estimation for Non-Random Functional Input Sequences. | Soumitra Bose, Vishwani D. Agrawal |
| 2006 | VTS | Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. | Vishwani D. Agrawal, Soumitra Bose, Vijay Gangaram |
| 2005 | DATE | Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. | Raja K. K. R. Sandireddy, Vishwani D. Agrawal |
| 2005 | ICCD | Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. | Fei Hu, Vishwani D. Agrawal |
| 2005 | ITC | A random access scans architecture to reduce hardware overhead. | Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh |
| 2005 | VLSID | Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. | Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
| 2005 | VLSID | Variable Input Delay CMOS Logic for Low Power Design. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2004 | ITC | On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. | Junwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal |
| 2004 | VLSID | A Tuturial on the Emerging Nanotechnology Devices. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2004 | VLSID | CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | ITC | Fault Collapsing via Functional Dominance. | Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre |
| 2003 | VLSID | Exclusive Test and its Applications to Fault Diagnosis. | Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja |
| 2003 | VLSID | A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. | Vishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | VLSID | Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. | Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell |
| 2003 | VLSID | New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. | Lan Rao, Michael L. Bushnell, Vishwani D. Agrawal |
| 2002 | ITC | A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. | A. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre |
| 2002 | ITC | Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. | Aditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal |
| 2002 | VLSID | Electronic Testing for SOC Designers (Tutorial Abstract). | Vishwani D. Agrawal, Michael L. Bushnell |
| 2002 | VLSID | Multiple Faults: Modeling, Simulation and Test. | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
| 2001 | DATE | Efficient spectral techniques for sequential ATPG. | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
| 2001 | ITC | Combinational test generation for various classes of acyclic sequential circuits. | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
| 2001 | VLSID | Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. | Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal |
| 2001 | VTS | Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. | Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal |
| 2000 | ASPDAC | A testability metric for path delay faults and its application. | Huan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal |
| 2000 | DATE | Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. | Jos T. de Sousa, Vishwani D. Agrawal |
| 2000 | ITC | Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
| 2000 | VLSID | Choice of Tests for Logic Verification and Equivalence Checking. | Vishwani D. Agrawal |
| 1999 | ITC | Panel: Increasing test coverage in a VLSI desgin course. | Vishwani D. Agrawal |
| 1999 | VLSID | Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. | Vishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss |
| 1999 | VLSID | A Test Generator for Segment Delay Faults. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1999 | VLSID | A Complete Characterization of Path Delay Faults through Stuck-at Faults. | Subhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell |
| 1999 | VTS | Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. | Pradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul |
| 1998 | ITC | A non-enumerative path delay fault simulator for sequential circuits. | Carlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu |
| 1998 | VLSID | Optimizing Logic Design Using Boolean Transforms. | Pramit Chavda, James Jacob, Vishwani D. Agrawal |
| 1998 | VLSID | Mixed-Signal Test. | Ananta K. Majhi, Vishwani D. Agrawal |
| 1998 | VLSID | Tutorial: Delay Fault Models and Coverage. | Ananta K. Majhi, Vishwani D. Agrawal |
| 1998 | VLSID | Path Delay Testing: Variable-Clock Versus Rated-Clock. | Subhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal |
| 1998 | VTS | On Delay-Untestable Paths and Stuck-Fault Redundancy. | Subhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell |
| 1997 | ICCAD | Fast identification of untestable delay faults using implications. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1997 | ITC | Algorithms for Switch Level Delay Fault Simulation. | Soumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski |
| 1997 | ITC | Effective Path Selection for Delay Fault Testing of Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1997 | VLSID | Low-Power Design by Hazard Filtering. | Vishwani D. Agrawal |
| 1997 | VLSID | Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. | James Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal |
| 1997 | VLSID | Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. | Mandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal |
| 1997 | VTS | Power Dissipation During Testing: Should We Worry About it? | Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian |
| 1996 | ICCAD | SIGMA: a simulator for segment delay faults. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | ITC | Synthesis of Self-Testing Finite State Machines from High-Level Specifications. | Vishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani |
| 1996 | ITC | An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | VLSID | Science, Technology, and the Indian Society. | Vishwani D. Agrawal |
| 1996 | VLSID | Characteristic polynomial method for verification and test of combinational circuits. | Vishwani D. Agrawal, David Lee |
| 1996 | VLSID | Design for high-speed testability of stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1996 | VLSID | Parallel concurrent path-delay fault simulation using single-input change patterns. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1996 | VLSID | Improving accuracy in path delay fault coverage estimation. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1996 | VLSID | On test coverage of path delay faults. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1996 | VLSID | Statistical path delay fault coverage estimation for synchronous sequential circuits. | Lakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas |
| 1996 | VTS | Segment delay faults: a new fault model. | Keerthi Heragu, Janak H. Patel, Vishwani D. Agrawal |
| 1995 | ITC | High-Performance Circuit Testing with Slow-Speed Testers. | Vishwani D. Agrawal, Tapan J. Chakraborty |
| 1995 | ITC | Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
| 1995 | VLSID | Robust testing for stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1995 | VLSID | Statistical methods for delay fault coverage analysis. | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
| 1995 | VLSID | An efficient automatic test generation system for path delay faults in combinational circuits. | Ananta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal |
| 1995 | VLSID | An asynchronous algorithm for sequential circuit test generation on a network of workstations. | James Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal |
| 1995 | VLSID | Functional test generation for non-scan sequential circuits. | Mandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal |
| 1995 | VTS | Simulation of at-speed tests for stuck-at faults. | Tapan J. Chakraborty, Vishwani D. Agrawal |
| 1994 | DAC | An Exact Algorithm for Selecting Partial Scan Flip-Flops. | Srimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal |
| 1994 | DAC | An Efficient Path Delay Fault Coverage Estimator. | Keerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal |
| 1994 | VLSID | Power Constraint Scheduling of Tests. | Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal |
| 1994 | VLSID | A Test Function Architecture for Interconnected Finite State Machines. | Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal |
| 1994 | VLSID | An Improved Deductive Fault Simulator. | P. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal |
| 1994 | VTS | FACTS: fault coverage estimation by test vector sampling. | Keerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell |
| 1993 | DAC | Sequential Circuit Test Generation on a Distributed System. | Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo |
| 1993 | DAC | Design for Testability for Path Delay faults in Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1993 | HPDC | Test Pattern Generation for Sequential Circuits on a Network of Workstations. | Prathima Agrawal, Vishwani D. Agrawal, Joan Villoldo |
| 1993 | ITC | Generation of Compact Delay Tests by Multiple-Path Activation. | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
| 1993 | ITC | A Synthesis Approach to Design for Testability. | Suman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal |
| 1993 | VLSID | A Path Delay Fault Simulator for Sequential Circuits. | Soumitra Bose, Prathima Agrawal, Vishwani D. Agrawal |
| 1993 | VTS | Partial scan testing with single clock control. | Vishwani D. Agrawal, Tapan J. Chakraborty |
| 1992 | DAC | Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. | Debashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal |
| 1992 | DAC | Delay Fault Models and Test Generation for Random Logic Sequential Circuits. | Tapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell |
| 1992 | DAC | Finite State Machine Synthesis with Fault Tolerant Test Function. | Srimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal |
| 1992 | VLSID | A New Method for Generating Tests for Delay Faults in Non-Scan Circuits. | Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth |
| 1992 | VLSID | Functional Test Generation for Sequential Circuits. | James Jacob, Vishwani D. Agrawal |
| 1991 | DAC | A Transitive Closure Based Algorithm for Test Generation. | Srimat T. Chakradhar, Vishwani D. Agrawal |
| 1991 | ICCD | Design and Test-The Two Sides of a Coin. | Vishwani D. Agrawal |
| 1991 | ICCD | Stafan Algorithms for MOS Circuits. | Joan Villoldo, Prathima Agrawal, Vishwani D. Agrawal |
| 1991 | ITC | Estimating the Quality of Manufactured Digital Sequential Circuits. | Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal |
| 1990 | DAC | Test Function Specification in Synthesis. | Vishwani D. Agrawal, Kwang-Ting Cheng |
| 1990 | DAC | Automatic Test Generation Using Quadratic 0-1 Programming. | Srimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell |
| 1990 | DAC | An Entropy Measure for the Complexity of Multi-Output Boolean Functions. | Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1990 | ICCAD | Logic Simulation and Parallel Processing. | Vishwani D. Agrawal, Srimat T. Chakradhar |
| 1990 | ITC | An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. | Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal |
| 1990 | SC | Performance estimation in a massively parallel system. | Vishwani D. Agrawal, Srimat T. Chakradhar |
| 1989 | ICCAD | State assignment for initializable synthesis (gate level analysis). | Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1989 | ICCAD | Design of sequential machines for efficient test generation. | Kwang-Ting Cheng, Vishwani D. Agrawal |
| 1989 | ITC | Fault Simulation in a Pipelined Multiprocessor System. | Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, Raffi Tutundjian |
| 1988 | DAC | Contest: A Concurrent Test Generator for Sequential Circuits. | Vishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal |
| 1988 | ICCAD | Automatic test generation using neural networks. | Srimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal |
| 1988 | ICCD | Test generation by fault sampling. | Vishwani D. Agrawal, Hassan Farhat, Sharad Seth |
| 1986 | ITC | Deterministic Versus Random Testing. | Vishwani D. Agrawal, M. Ray Mercer |
| 1985 | DAC | Multiple output minimization. | Prathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas |
| 1985 | ITC | STAFAN Takes a Middle Course. | Vishwani D. Agrawal |
| 1984 | DAC | Chip layout optimization using critical path weighting. | Alfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel |
| 1984 | DAC | STAFAN: An alternative to fault simulation. | Sunil K. Jain, Vishwani D. Agrawal |
| 1984 | DAC | A gate level model for CMOS combinational logic circuits with application to fault detection. | Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain |
| 1984 | ITC | Will Testability Analysis Replace Fault Simulation ? | Vishwani D. Agrawal |
| 1983 | DAC | Test generation for MOS circuits using D-algorithm. | Sunil K. Jain, Vishwani D. Agrawal |
| 1982 | DAC | Synchronous path analysis in MOS circuit simulator. | Vishwani D. Agrawal |
| 1982 | ITC | Testability Measures : What Do They Tell Us ? | Vishwani D. Agrawal, M. Ray Mercer |
| 1981 | DAC | LSI product quality and fault coverage. | Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal |
| 1981 | ITC | Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. | M. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman |
| 1980 | DAC | A mixed-mode simulator. | Vishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes |