| 2020 | VLSID | Fault Tolerance through Invariant Checking for the Lanczos Eigensolver. | Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan |
| 2018 | SC | Fault Tolerant Cholesky Factorization on GPUs. | Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan |
| 2017 | ITC | Exploiting path delay test generation to develop better TDF tests for small delay defects. | Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja |
| 2016 | VLSID | Fault Tolerance through Invariant Checking for Iterative Solvers. | Felix Loh, Kewal K. Saluja, Parameswaran Ramanathan |
| 2016 | VLSID | Digital Testing - Basics to Advanced Research Issues. | Kewal K. Saluja |
| 2015 | COMPSAC | Privacy Assurance in Data-Aggregation for Multiple MAX Transactions. | Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja |
| 2015 | HPDC | Transient Fault Resilient QR Factorization on GPUs. | Felix Loh, Parameswaran Ramanathan, Kewal K. Saluja |
| 2015 | VLSID | Thermal Extension of the Total Bandwidth Server. | Rehan Ahmed, Ayoosh Bansal, Bhuvana Kakunoori, Parameswaran Ramanathan, Kewal K. Saluja |
| 2015 | VLSID | Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. | Spencer K. Millican, Kewal K. Saluja |
| 2014 | ECRTS | Necessary and Sufficient Conditions for Thermal Schedulability of Periodic Real-Time Tasks. | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja |
| 2014 | VLSID | Temperature Minimization Using Power Redistribution in Embedded Systems. | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja |
| 2014 | VLSID | CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. | Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja |
| 2014 | VLSID | A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. | Spencer K. Millican, Kewal K. Saluja |
| 2013 | ICISC | Privacy Assurances in Multiple Data-Aggregation Transactions. | Kim T. Le, Parmesh Ramanathan, Kewal K. Saluja |
| 2013 | VLSID | Scheduling Aperiodic Tasks in Next Generation Embedded Real-Time Systems. | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja, Chunhua Yao |
| 2013 | RTCSA | On thermal utilization of periodic task sets in uni-processor systems. | Rehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja |
| 2012 | PRDC | Diagnosis for Bridging Faults on Clock Lines. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2012 | VLSID | Impact of Body Bias Based Leakage Power Reduction on Soft Error Rate. | Warin Sootkaneung, Kewal K. Saluja |
| 2011 | ASPDAC | Fault simulation and test generation for clock delay faults. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2011 | DDECS | Indirect detection of clock skew induced hold-time violations on functional paths using scan shift operations. | Tsuyoshi Iwagaki, Kewal K. Saluja |
| 2011 | ETS | Enhancement of Clock Delay Faults Testing. | Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja |
| 2011 | ICCD | Adaptive execution assistance for multiplexed fault-tolerant chip multiprocessors. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2011 | VLSID | Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
| 2010 | DAC | Post-silicon diagnosis of segments of failing speedpaths due to manufacturing variations. | Lin Xie, Azadeh Davoodi, Kewal K. Saluja |
| 2010 | DATE | Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2010 | DSN | Gate input reconfiguration for combating soft errors in combinational circuits. | Warin Sootkaneung, Kewal K. Saluja |
| 2010 | DSN | Energy-efficient fault tolerance in chip multiprocessors using Critical Value Forwarding. | Pramod Subramanyan, Virendra Singh, Kewal K. Saluja, Erik Larsson |
| 2010 | ETS | Modified T-Flip-Flop based scan cell for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | ISCAS | Test application time minimization for RAS using basis optimization of column decoder. | A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh |
| 2010 | ISCAS | Detection of inter-port bridging faults in dual-port memories. | Ho-Yong Choi, Kewal K. Saluja |
| 2010 | ITC | On techniques for handling soft errors in digital circuits. | Warin Sootkaneung, Kewal K. Saluja |
| 2010 | VLSID | On Minimization of Test Application Time for RAS. | Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh |
| 2010 | SECON | Connected Barrier Coverage on a Narrow Band: Analysis and Deployment. | Yen-Ting Lin, Kewal K. Saluja, Parameswaran Ramanathan |
| 2009 | ITC | Power and thermal constrained test scheduling. | Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan |
| 2009 | VLSID | WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements. | Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar |
| 2009 | VTS | False Path Aware Timing Yield Estimation under Variability. | Lin Xie, Azadeh Davoodi, Kewal K. Saluja, Abhishek A. Sinkar |
| 2009 | SECON | Blindly Calibrating Mobile Sensors Using Piecewise Linear Functions. | Chao Wang, Parmesh Ramanathan, Kewal K. Saluja |
| 2008 | DSN | An accurate flip-flop selection technique for reducing logic SER. | Eric L. Hill, Mikko H. Lipasti, Kewal K. Saluja |
| 2008 | ETS | A Capture-Safe Test Generation Scheme for At-Speed Scan Testing. | Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja |
| 2008 | MICRO | Implementing high availability memory with a duplication cache. | Nidhi Aggarwal, James E. Smith, Kewal K. Saluja, Norman P. Jouppi, Parthasarathy Ranganathan |
| 2008 | VLSID | Testing Flash Memories for Tunnel Oxide Defects. | Mohammad Gh. Mohammad, Kewal K. Saluja |
| 2008 | VLSID | NBTI Degradation: A Problem or a Scare? | Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang |
| 2008 | SECON | Calibrating Nonlinear Mobile Sensors. | Chao Wang, Parmesh Ramanathan, Kewal K. Saluja |
| 2007 | DAC | Critical-Path-Aware X-Filling for Effective IR-Drop Reduction in At-Speed Scan Testing. | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Seiji Kajihara, Yuji Ohsumi, Kewal K. Saluja |
| 2007 | VLSID | Fault Coverage and Fault Efficiency of Transistor Shorts using Gate-Level Simulation and Test Generation. | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Yuzo Takamatsu |
| 2007 | VLSID | Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan. | Kim T. Le, Dong Hyun Baik, Kewal K. Saluja |
| 2007 | VLSID | On NBTI Degradation Process in Digital Logic Circuits. | Xiangning Yang, Eric F. Weglarz, Kewal K. Saluja |
| 2006 | ASPDAC | Compaction of pass/fail-based diagnostic test vectors for combinational and sequential circuits. | Yoshinobu Higami, Kewal K. Saluja, Hiroshi Takahashi, Shin-ya Kobayashi, Yuzo Takamatsu |
| 2006 | GLOBECOM | Optimal Sensor Distribution for Maximum Exposure in A Region with Obstacles. | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja |
| 2006 | ICCD | Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation. | Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja |
| 2006 | VLSID | Test Cost Reduction Using Partitioned Grid Random Access Scan. | Dong Hyun Baik, Kewal K. Saluja |
| 2006 | VTS | A New ATPG Method for Efficient Capture Power Reduction During Scan Testing. | Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Tatsuya Suzuki, Kewal K. Saluja, Laung-Terng Wang, Khader S. Abdel-Hafez, Kozo Kinoshita |
| 2005 | FPL | Testing Superscalar Processors in Functional Mode. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ISCAS | Instruction-based delay fault self-testing of pipelined processor cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ITC | Progressive random access scan: a simultaneous solution to test power, test data volume and test time. | Dong Hyun Baik, Kewal K. Saluja |
| 2005 | ITC | Design and analysis of multiple weight linear compactors of responses containing unknown values. | Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara |
| 2005 | ITC | Low-capture-power test generation for scan-based at-speed testing. | Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2005 | MASS | Exposure for collaborative detection using mobile sensor networks. | Tai-Lin Chin, Parameswaran Ramanathan, Kewal K. Saluja, Kuang-Ching Wang |
| 2005 | VLSID | SCINDY: Logic Crosstalk Delay Fault Simulation in Sequential Circuits. | Marong Phadoongsidhi, Kewal K. Saluja |
| 2005 | VLSID | False Path and Clock Scheduling Based Yield-Aware Gate Sizing. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
| 2005 | VTS | On Low-Capture-Power Test Generation for Scan Testing. | Xiaoqing Wen, Yoshiyuki Yamashita, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2004 | ETS | Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. | Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy |
| 2004 | ICCAD | A yield improvement methodology using pre- and post-silicon statistical clock scheduling. | Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja |
| 2004 | ICCAD | On per-test fault diagnosis using the X-fault model. | Xiaoqing Wen, Tokiharu Miyoshi, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita |
| 2004 | IOLTS | Testing of Hard Faults in Simultaneous Multithreaded Processors. | Eric F. Weglarz, Kewal K. Saluja, T. M. Mak |
| 2004 | ITC | Testing Micropipelined Asynchronous Circuits. | Matthew L. King, Kewal K. Saluja |
| 2004 | VLSID | Random Access Scan: A solution to test power, test data volume and test time. | Dong Hyun Baik, Kewal K. Saluja, Seiji Kajihara |
| 2004 | VLSID | Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. | Marong Phadoongsidhi, Kewal K. Saluja |
| 2004 | VLSID | Instruction-Based Delay Fault Self-Testing of Processor Cores. | Virendra Singh, Michiko Inoue, Kewal K. Saluja, Hideo Fujiwara |
| 2003 | ICCD | Event-Centric Simulation of Crosstalk Pulse Faults in Sequential Circuits. | Marong Phadoongsidhi, Kewal K. Saluja |
| 2003 | VLSID | Exclusive Test and its Applications to Fault Diagnosis. | Vishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja |
| 2003 | VLSID | Electrical Model For Program Disturb Faults in Non-Volatile Memories. | Mohammad Gh. Mohammad, Kewal K. Saluja |
| 2002 | MOBICOM | Sensor deployment strategy for target detection. | Thomas Clouqueur, Veradej Phipatanasuphorn, Parameswaran Ramanathan, Kewal K. Saluja |
| 2002 | PRDC | An Alternative Method of Generating Tests for Path Delay Faults Using N -Detection Test Sets. | Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
| 2002 | VLSID | Multiple Faults: Modeling, Simulation and Test. | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
| 2002 | VLSID | Estimation of Maximum Power-Up Current. | Fei Li, Lei He, Kewal K. Saluja |
| 2002 | VLSID | Minimizing Energy Consumption for High-Performance Processing. | Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti |
| 2001 | ITC | On reducing the target fault list of crosstalk-induced delay faults in synchronous sequential circuits. | Keith J. Keller, Hiroshi Takahashi, Kewal K. Saluja, Yuzo Takamatsu |
| 2001 | ITC | Combinational test generation for various classes of acyclic sequential circuits. | Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja |
| 2001 | VLSID | Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. | Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi |
| 2001 | VLSID | Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. | Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal |
| 2001 | VTS | Testable Sequential Circuit Design: A Partition and Resynthesis Approach. | Richard M. Chou, Kewal K. Saluja |
| 2001 | VTS | Flash Memory Disturbances: Modeling and Test. | Mohammad Gh. Mohammad, Kewal K. Saluja |
| 2000 | ASPDAC | Fault models and test generation for IDDQ testing: embedded tutorial. | Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita |
| 2000 | DSN | Fault Tolerance through Re-Execution in Multiscalar Architecture. | Faisal Rashid, Kewal K. Saluja, Parameswaran Ramanathan |
| 2000 | VLSID | Testing Flash Memories. | Mohammad Gh. Mohammad, Kewal K. Saluja, Alex S. Yap |
| 2000 | VLSID | Design for Strong Testability of RTL Data Paths to Provide Complete Fault Efficiency. | Hiroki Wada, Toshimitsu Masuzawa, Kewal K. Saluja, Hideo Fujiwara |
| 1999 | VLSID | Efficient Techniques for Reducing IDDQ Observation Time for Sequential Circuits. | Yoshinobu Higami, Kewal K. Saluja, Kozo Kinoshita |
| 1998 | VLSID | On Test Pattern Compaction Using Random Pattern Fault Simulation. | Seiji Kajihara, Kewal K. Saluja |
| 1997 | VLSID | Sequential Circuit Testing: From DFT to SFT. | Richard M. Chou, Kewal K. Saluja |
| 1996 | ICCAD | A new method towards achieving global optimality in technology mapping. | Xiaoqing Wen, Kewal K. Saluja |
| 1996 | VLSID | Methods for Dynamic Test Vector compaction in Sequential Test Generation. | Timothy John Lambert, Kewal K. Saluja |
| 1995 | VLSID | Fast computation of MISR signatures. | Manoj Franklin, Kewal K. Saluja, Kyuchull Kim |
| 1995 | VTS | An optimized testable architecture for finite state machines. | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja |
| 1994 | VLSID | Power Constraint Scheduling of Tests. | Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal |
| 1994 | VLSID | An Algorithm to Test Reconfigured RAMs. | Manoj Franklin, Kewal K. Saluja |
| 1994 | VTS | Sequential test generation with reduced test clocks for partial scan designs. | Soo Young Lee, Kewal K. Saluja |
| 1993 | ISCAS | Efficient Test Vectors for ISCAS Sequential Benchmark Circuits. | Soo Young Lee, Kewal K. Saluja |
| 1993 | VTS | CCSTG: an efficient test pattern generator for sequential circuits. | Kyuchull Kim, Kewal K. Saluja |
| 1992 | ICCAD | An algorithm to reduce test application time in full scan designs. | Soo Young Lee, Kewal K. Saluja |
| 1992 | VLSID | An Efficient Method for Computation of Signatures. | Chin-Foo See, Kewal K. Saluja |
| 1992 | VTS | On fault deletion problem in concurrent fault simulation for synchronous sequential circuits. | Kyuchull Kim, Kewal K. Saluja |
| 1992 | VTS | Zero cost testing of check bits in RAMs with on-chip ECC. | Parameswaran Ramanathan, Kewal K. Saluja, Michael J. Franklin |
| 1991 | ITC | An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. | Manoj Franklin, Kewal K. Saluja |
| 1989 | ICCAD | Fast test generation for sequential circuits. | Todd P. Kelsey, Kewal K. Saluja |
| 1989 | ITC | Design of a BIST RAM with Row/Column Pattern Sensitive Fault Detection Capability. | Manoj Franklin, Kewal K. Saluja, Kozo Kinoshita |
| 1987 | DAC | BIST-PLA: A Built-in Self-Test Design of Large Programmable Logic Arrays. | Chun-Yeh Liu, Kewal K. Saluja, Shambhu J. Upadhyaya |
| 1987 | ISCA | Organization and Analysis of a Gracefully-Degrading Interleaved Memory System. | Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan |
| 1986 | ITC | A Novel Approach for Testing Memories Using a Built-In Self Testing Technique. | Kim T. Le, Kewal K. Saluja |
| 1985 | ITC | A Testable Design of Programmable Logic Arrays with Universal Control and Minimal Overhead. | Hideo Fujiwara, Kewal K. Saluja, Kozo Kinoshita |
| 1984 | ITC | Built-in Testing of Memory Using On-chip Compact Testing Scheme. | Kozo Kinoshita, Kewal K. Saluja |
| 1983 | ITC | Testing Computer Hardware through Data Compression in Space and Time. | Kewal K. Saluja, Mark G. Karpovsky |
| 1983 | ITC | A Simplified Algorithm for Testing Microprocessors. | Kewal K. Saluja, Li Shen, Stephen Y. H. Su |
| 1982 | DAC | An enhancement of lssd to reduce test pattern generation effort and increase fault coverage. | Kewal K. Saluja |
| 1972 | FOCS | Multiple Faults in Reed-Muller Canonic Networks | Kewal K. Saluja, Sudhakar M. Reddy |